Receiver with enhanced clock and data recovery

An integrated circuit comprising:

• a receiver to receive a data signal, the receiver having a data sampler and an edge sampler;
• circuitry to generate a recovered clock from the data signal depending on outputs of the data sampler and the edge sampler;
• a first clock phase adjustment loop to adjust phase of an edge sampling clock for the edge sampler so as to align with expected symbol transition times of the data signal, the edge sampling clock being derived from the recovered clock;
• a second clock phase adjustment loop to adjust phase of a data sampling clock for the data sampler, the data sampling clock also being derived from the recovered clock;
• wherein the first circuitry and the second circuitry are to adjust phase independently of each other.

An integrated circuit comprising:

• a receiver to receive a data signal, the receiver having a data sampler and an edge sampler;
• circuitry to generate a recovered clock from the data signal depending on outputs of the data sampler and the edge sampler;
• a first clock phase adjustment loop to adjust phase of an edge sampling clock for the edge sampler so as to align with expected symbol transition times of the data signal, the edge sampling clock being derived from the recovered clock;
• a second clock phase adjustment loop to adjust phase of a data sampling clock for the data sampler, the data sampling clock also being derived from the recovered clock;
• wherein the first circuitry and the second circuitry are to adjust phase independently of each other;
• and
• wherein the data sampler comprises a flash analog-to-digital converter.

An integrated circuit comprising:

• a receiver to receive a data signal, the receiver having a data sampler and an edge sampler;
• circuitry to generate a recovered clock from the data signal depending on outputs of the data sampler and the edge sampler;
• a first clock phase adjustment loop to adjust phase of an edge sampling clock for the edge sampler so as to align with expected symbol transition times of the data signal, the edge sampling clock being derived from the recovered clock;
• a second clock phase adjustment loop to adjust phase of a data sampling clock for the data sampler, the data sampling clock also being derived from the recovered clock;
• wherein the first circuitry and the second circuitry are to adjust phase independently of each other;
• and
• wherein an update rate of the second clock phase adjustment control loop is slower than an update rate of the first clock phase adjustment control loop.