Method and apparatus for synchronous signaling between link partners in a high-speed interconnect
AssigneeIntel Corporation
InventorsAdee Ofir RAN, Kent C. LUSTED
Life of this patent
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Abstract
Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave.
Claims28
An apparatus comprising:
- port circuitry in a slave link partner, to communicate with a master link partner, the port circuitry including:
- a transmit clock having a transmit clock frequency;
- and
- a loop timing controller configured to receive a recovered receive clock from the master link partner and to initialize loop timing with the master link partner to adjust the transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency.
A system comprising:
- a slave link partner;
- port circuitry in the slave link partner, to communicate via a copper cable with a master link partner, the port circuitry including:
- a transmit clock having a transmit clock frequency;
- and
- a loop timing controller configured to receive a recovered receive clock from the master link partner and to initialize loop timing with the master link partner to adjust the transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency.
A method comprising:
- communicating by port circuitry in a slave link partner with a master link partner;
- receiving a recovered receive clock from the master link partner;
- and
- initializing loop timing, by a loop timing controller, with the master link partner to adjust a transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency.
A system comprising:
- a memory module, the memory module comprising at least one volatile memory integrated circuit, the volatile memory integrated circuit to store a message;
- and
- port circuitry in a slave link partner, to send the message stored in the volatile memory integrated circuit to a master link partner, the port circuitry including:
- a transmit clock having a transmit clock frequency;
- and
- a loop timing controller configured to receive a recovered receive clock from the master link partner and to initialize loop timing with the master link partner to adjust the transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency.
An apparatus comprising:
- a transmit clock having a transmit clock frequency;
- and
- a loop timing controller configured to adjust the transmit clock frequency to be equal to a receive clock frequency of a recovered receive clock for a PHY.
A machine-readable medium for storing machine-executable instructions that, cause a system to:
- send, from a slave link partner, a Link-Layer Discovery Protocol (LLDP) frame to a master link partner, the frame to include a loop timing message that includes a control, length, and value (TLV) information string with message type bits set to indicate the slave link partner is a timing slave;
- and
- in response to an acknowledge message received from the master link partner, activate loop timing with the slave link partner as the timing slave.
Dependencies are inferred from the claim text.