US 2020/0052707 A1 · CLOCK GENERATION SYSTEM AND METHOD HAVING TIME AND FREQUENCY DIVISION ACTIVATION MECHANISM

Abstract

A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.

Claims12

Dependent claims

A clock generation system having a time and frequency division activation mechanism comprising:

a clock source processing circuit configured to generate a primary clock signal;
and
a plurality of clock-branching circuits that perform a clock-branching generation procedure respectively in an order each comprising:
a frequency division unit, during the clock-branching generation procedure, configured to receive the primary clock signal to divide a frequency of the primary clock signal according to a divisor number and output a branch clock signal;
and
a processing unit configured to control the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over the time period from an initial divisor number larger than one to a final divisor number after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.

3 more elements

A clock generation method having a time and frequency division activation mechanism comprising:

generating a primary clock signal by a clock source processing circuit;
controlling a frequency division unit comprised in each of a plurality of clock-branching circuits to not output a branch clock signal before a clock-branching generation procedure by a processing unit comprised in each of the clock-branching circuits;
and
performing the clock-branching generation procedure respectively in an order by the clock-branching circuits, wherein the clock-branching generation procedure comprises:
receiving the primary clock signal to divide a frequency of the primary clock signal according to a divisor number and output a branch clock signal by the frequency division unit;
and
decreasing the divisor number gradually over the time period from an initial divisor number larger than one to a final divisor number such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure by the processing unit.

4 more elements

Dependencies are inferred from the claim text.

Clock generation system and method having time and frequency division activation mechanism

Life of this patent

Clock generation system and method having time and frequency division activation mechanism

Life of this patent

Abstract

Claims12