A level shifter, comprising:
- a first strong driving path;
- a first weak driving path;
- a second strong driving path;
- a second weak driving path;
- a selecting module comprising a first selecting circuit and a second selecting circuit, wherein the first strong driving path is connected between a power supply voltage and a first input terminal of the first selecting circuit, the first weak driving path is connected between the power supply voltage and a second input terminal of the first selecting circuit, the second strong driving path is connected between the power supply voltage and a first input terminal of the second selecting circuit, and the second weak driving path is connected between the power supply voltage and a second input terminal of the second selecting circuit;
- a first P-type transistor, wherein a source terminal of the first P-type transistor is connected with an output terminal of the second selecting circuit, a drain terminal of the first P-type transistor is connected with a first node, and a gate terminal of the first P-type transistor is connected with a second node;
- a second P-type transistor, wherein a source terminal of the second P-type transistor is connected with an output terminal of the first selecting circuit, a drain terminal of the second P-type transistor is connected with the second node, and a gate terminal of the second P-type transistor is connected with the first node, wherein the second node generates an output signal, and the first node generates an inverted output signal;
- a first N-type transistor, wherein a drain terminal of the first N-type transistor is connected with the first node, a source terminal of the first N-type transistor is connected with a ground terminal, and a gate terminal of the first N-type transistor receives an input signal;
- a second N-type transistor, wherein a drain terminal of the second N-type transistor is connected with the second node, a source terminal of the second N-type transistor is connected with the ground terminal, and a gate terminal of the second N-type transistor receives an inverted input signal, wherein when the input signal is in a first high level state, the output signal is in a second high level state, wherein when the input signal is in a low level state, the output signal is in the low level state;
- and
- a timing controller receiving one of the output signal and the inverted output signal or receiving both of the output signal and the inverted output signal, wherein the timing controller issues a control signal group to the selecting module, and the first selecting circuit and the second selecting circuit are controlled according to the control signal group,
- wherein after the output signal and the inverted output signal are respectively changed to the second high level state and the low level state for a time period, the first weak driving path is connected with the source terminal of the second P-type transistor by the first selecting circuit, and the second strong driving path is connected with the source terminal of the first P-type transistor by the second selecting circuit,
- wherein after the output signal and the inverted output signal are respectively changed to the low level state and the second high level state for the time period, the first strong driving path is connected with the source terminal of the second P-type transistor by the first selecting circuit, and the second weak driving path is connected with the source terminal of the first P-type transistor by the second selecting circuit.