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US 2020/0052702 A1Published application
Complementary logic circuit and application to thin-film hybrid electronics
AssigneeInternational Business Machines Corporation
InventorsBahman Hekmatshoartabari, Ghavam G. Shahidi
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Abstract
A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.
Claims3
A complementary circuit, comprising:
- a logic unit configured to provide a logic function and a digital operation comprising pull-up depletion-mode circuit MOS transistors and pull-down depletion-mode MOS transistors;
- and
- a level shifting circuit including diodes which are implemented by a circuitry arrangement of a heterojunction field-effect transistor (HJFET) device,
- wherein the pull-up transistors and the pull-down transistors comprise transistors both n-channel or comprise both p-channel transistors, and
- wherein the level shifting circuit is coupled to the logic unit.
2 more elements
A system, comprising:
- a circuit comprising a heterojunction field-effect transistor (HJFET) device and a depletion-mode MOS device;
- and
- a complementary circuit coupled to the circuit, the complementary circuit including:
- a logic unit configured to provide a logic function and a digital operation comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors;
- and
- a level shifting circuit including diodes which are implemented by a circuitry arrangement of the heterojunction field-effect transistor (HJFET) device,
- wherein the pull-up transistors and the pull-down transistors comprise both n-channel transistors or comprise both p-channel transistors, and
- wherein the level shifting circuit is coupled to the logic unit.
5 more elements
An active matrix display, comprising:
- a row driver implemented using a complementary circuit, the complementary circuit including:
- a logic unit configured to provide a logic function and a digital operation comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors;
- and
- a level shifting circuit including diodes which are implemented by a circuitry arrangement of a heterojunction field-effect transistor (HJFET) device,
- wherein the pull-up transistors and the pull-down transistors comprise both n-channel transistors or comprise both p-channel transistors, and
- wherein the level shifting circuit is coupled to the logic unit.
3 more elements
Dependencies are inferred from the claim text.