Clock circuit having a pulse width adjustment module

A clock circuit having a clock input terminal and a clock output terminal, wherein the clock input terminal receives an input clock signal, and the clock output terminal outputs an output clock signal, the clock circuit comprising:

• a first inverter including a first terminal, and a second terminal, the first terminal of the first inverter electrically connected to the clock input terminal, and the second terminal of the first inverter electrically connected to the clock output terminal;
• a second inverter including a first terminal and a second terminal, the first terminal of the second inverter electrically connected to the clock input terminal;
• a pulse width adjustment module including a pulse width input terminal, a control terminal, a power terminal, a ground terminal, and a pulse width output terminal, the pulse width input terminal electrically connected to the clock input terminal to receive the input clock signal through the second inverter and a buffer circuit, and the power terminal electrically connected to a first reference voltage;
• a sampling module including a first terminal and a second terminal, the first terminal of the sampling terminal electrically connected to the clock output terminal of the clock circuit, the sampling module used for sampling an output voltage of the clock output terminal of the clock circuit to generate a first sampling voltage;
• and
• a comparing module including a first comparing input terminal, a second comparing input terminal, and a comparing output terminal, the first comparing input terminal electrically connected to a comparing reference voltage, the second comparing input terminal electrically connected to the second terminal of the sampling module, and the comparing output terminal electrically connected to the control terminal of the pulse width adjustment module;
• wherein the second terminal of the second inverter is electrically connected to the pulse width input terminal of the pulse width adjustment module.

A clock circuit having a first clock input terminal, a second clock input terminal, a first clock output terminal, and a second clock output terminal, wherein the first clock input terminal receives a first input clock signal, the second clock input terminal receives a second input clock signal, and the first clock output terminal and the second clock output terminal outputs output clock signals, the clock circuit comprising:

• a first clock inverter including a first terminal and a second terminal, the first terminal of the first clock inverter electrically connected to the first clock input terminal, the second terminal of the first clock inverter electrically connected to the first clock output terminal;
• a second clock inverter including a first terminal and a second terminal, the first terminal of the second clock inverter electrically connected to the second clock input terminal, and the second terminal of the second clock inverter electrically connected to the second clock output terminal;
• a first pulse width adjustment module including a first pulse width input terminal, a first control terminal, a first power terminal, a first ground terminal, and a first pulse width output terminal, the first pulse width input terminal receiving the first input clock signal, the first power terminal electrically connected to a first reference voltage, the first ground terminal electrically connected to a ground voltage, and the first pulse width output terminal electrically connected to the second clock output terminal;
• a second pulse width adjustment module including a second pulse width input terminal, a second control terminal, a second power terminal, a second ground terminal, and a second pulse width output terminal, the second pulse width input terminal receiving the second clock input terminal, the second power terminal electrically connected to a third reference voltage, the second ground terminal electrically connected to a fourth reference voltage, and the second pulse width output terminal electrically connected to the first clock output terminal;
• a first sampling module including a first terminal and a second terminal, the first terminal of the first sampling module electrically connected to the first clock output terminal of the clock circuit, the first sampling module used for sampling an output voltage of the first clock output terminal of the clock circuit to generate a first sampling voltage;
• a second sampling module including a first terminal and a second terminal, the first terminal of the second sampling module electrically connected to the second clock output terminal of the clock circuit, the second sampling module used for sampling an output voltage of the second clock output terminal of the clock circuit to generate a second sampling voltage;
• a first comparing module including a first comparing input terminal, a second comparing input terminal, and a comparing output terminal, the first comparing input terminal of the first comparing module electrically connected to a first comparing reference voltage, the second comparing input terminal of the first comparing module electrically connected to the second terminal of the first sampling module, the second comparing input terminal receiving the first sampling voltage, the comparing output terminal of the first comparing module electrically connected to the first control terminal of the first pulse width adjustment module;
• and
• a second comparing module including a first comparing input terminal, a second comparing input terminal, and a comparing output terminal, the first comparing input terminal of the second comparing module electrically connected to a second comparing reference voltage, the second comparing input terminal of the second comparing module electrically connected to the second terminal of the second sampling module, the second comparing input terminal receiving the second sampling voltage, and the comparing output terminal of the second comparing module electrically connected to the second control terminal of the second pulse width adjustment module.