Synchronous mirror delay circuit and synchronous mirror delay operation method

A synchronous mirror delay (SMD) circuit, comprising:

• a delay monitor circuit (DMC), coupled to an input buffer;
• a forward delay circuit;
• a first shift circuit;
• coupled to the DMC and the forward delay circuit;
• a backward delay circuit;
• a second shift circuit, coupled to the backward delay circuit and a clock driver;
• and
• a clock-frequency-checker (CSC) circuit, coupled to the first shift circuit and the second shift circuit,
• wherein the CSC circuit determines whether the frequency of an external input clock signal is slower than the frequency of a reference clock signal to generate a judgment result, and the CSC circuit transmits the judgment result to the first shift circuit and the second shift circuit, and
• wherein the first shift circuit and the second shift circuit determine whether to delay the external input clock signal based on the judgment result.