Clock signal boost circuit
AssigneeAblic Inc.
InventorFumiyasu Utsunomiya
Life of this patent
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Abstract
A clock signal boost circuit includes a first NMOS transistor having a drain to a power terminal, a source to a first node, and a gate to a first terminal, a second NMOS transistor having a drain to the first node, a source to a GND, and a gate to a second terminal, a third NMOS transistor having a drain to the power terminal, a source to a second node, and a gate to the second terminal, a capacitor between the first node and the second node, a PMOS transistor having a source to the second node, a drain to an output terminal, and a gate to the second terminal, and a fourth NMOS transistor having a drain to the output terminal, a source to the GND, and a gate to the second terminal. The first and the third NMOS transistors are depletion type NMOS transistors.
Claims2
A clock signal boost circuit comprising:
- a first input terminal supplied with a first clock signal;
- a second input terminal supplied with a second clock signal having a negative phase to the first clock signal;
- a first NMOS transistor having a drain connected to a power supply terminal, a source connected to a first node, and a gate connected to the first input terminal;
- a second NMOS transistor having a drain connected to the first node, a source connected to a GND terminal, and a gate connected to the second input terminal;
- a third NMOS transistor having a drain connected to the power supply terminal, a source connected to a second node, and a gate connected to the second input terminal;
- a capacitor connected between the first node and the second node;
- a PMOS transistor having a source connected to the second node, a drain connected to an output terminal, and a gate connected to the second input terminal;
- and
- a fourth NMOS transistor having a drain connected to the output terminal, a source connected to the GND terminal, and a gate connected to the second input terminal,
- wherein the first NMOS transistor and the third NMOS transistor are depletion type NMOS transistors.
Dependencies are inferred from the claim text.