Switching layer scheme to enhance rram performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
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Abstract
The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.
Claims20
A resistive random access memory (RRAM) device, comprising:
- a first electrode over a substrate;
- a second electrode over the substrate;
- and
- a data storage structure disposed between the first electrode and the second electrode and comprising a plurality of sub-layers, wherein the plurality of sub-layers comprise one or more metals having non-zero concentrations that change as a distance from the first electrode increases.
A resistive random access memory (RRAM) device, comprising:
- a lower electrode over a substrate;
- an upper electrode over the lower electrode;
- and
- a data storage structure disposed between the lower electrode and the upper electrode and comprising a first sub-layer having a first oxygen vacancy density and a second sub-layer having a second oxygen vacancy density that is larger than the first oxygen vacancy density.
A method of forming a memory device, comprising:
- depositing a lower electrode structure over a substrate;
- depositing a plurality of sub-layers over the lower electrode structure, wherein the plurality of sub-layers comprise different non-zero concentrations of one or more metals from a first group of metals;
- depositing an upper electrode structure over the plurality of sub-layers;
- and
- patterning the upper electrode structure, the plurality of sub-layers, and the lower electrode structure to define a data storage layer between a lower electrode and an upper electrode.
Dependencies are inferred from the claim text.