Self-Aligned Spacers for Multi-Gate Devices and Method of Fabrication Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Abstract
A semiconductor device includes a substrate; a channel member above the substrate; a gate structure wrapping the channel member; a source/drain (S/D) feature abutting the channel member; and an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member.
Claims20
A semiconductor device, comprising:
- a substrate;
- a channel member above the substrate;
- a gate structure wrapping the channel member;
- a source/drain (S/D) feature abutting the channel member;
- and
- an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member.
A semiconductor device, comprising:
- a substrate;
- a plurality of nanosheets vertically stacked over each other and above the substrate;
- a gate structure disposed over a channel region of the plurality of nanosheets and surrounding each of the nanosheets;
- an epitaxial source/drain (S/D) feature adjacent the plurality of nanosheets;
- and
- a dielectric layer sandwiched between the epitaxial S/D feature and the gate structure and surrounding each of the nanosheets, wherein between two adjacent nanosheets the dielectric layer has a concave surface interfacing with the gate structure.
A multi-gate semiconductor device, comprising:
- a fin element extending upwardly from a substrate;
- a gate structure engaging the fin element;
- an epitaxial source/drain (S/D) feature in physical contact with the fin element;
- and
- a dielectric spacer interposing the gate structure and the epitaxial S/D feature, wherein a sidewall surface of the dielectric spacer facing the gate structure has a convex shape in a plane parallel to a top surface of the substrate, the convex shape having an apex extending towards the gate structure.
Dependencies are inferred from the claim text.