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US 2020/0052131 A1Published application
Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsI-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Carlos H. Diaz
Life of this patent
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Abstract
A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
Claims20
A semiconductor device comprising:
- a substrate;
- a plurality of nanowire structures over the substrate;
- a gate structure over the plurality of nanowire structures, wherein the gate structure extends between adjacent ones of the plurality of nanowire structure;
- upper spacers along sidewalls of the gate structure;
- source/drain regions on opposing sides of the gate structure, the source/drain regions contacting the plurality of nanowire structures;
- and
- inner spacers interposed between the source/drain regions and the gate structure, wherein a surface of the gate structure at an interface between the gate structure and each of the inner spacers is non-planar.
4 more elements
A semiconductor device comprising:
- a substrate;
- a plurality of semiconductor channel structures over the substrate;
- a gate structure over the plurality of semiconductor channel structures, wherein the gate structure extends between adjacent ones of the plurality of semiconductor channel structures;
- upper spacers along sidewalls of the gate structure;
- source/drain regions on opposing sides of the gate structure;
- and
- a plurality of inner spacers, each of the inner spacers being interposed between the adjacent ones of the plurality of semiconductor channel structures, each of the inner spacers being interposed between the source/drain regions and the gate structure, wherein sidewalls of the gate structure at an interface between the gate structure and each of the plurality of inner spacers is concave;
- and
- a plurality of voids, each of the voids being interposed between the source/drain regions and the gate structure.
6 more elements
A semiconductor device comprising:
- a first transistor on a substrate, the first transistor comprising:
- a plurality of first nanowire structures over the substrate, the plurality of first nanowire structures comprising a first semiconductor material;
- a first gate structure extending around the plurality of first nanowire structures, the first gate structure having non-planar sidewalls between adjacent ones of the plurality of first nanowire structures;
- a plurality of first inner spacers, each of the plurality of first inner spacers being formed along a corresponding one of the non-planar sidewalls of the first gate structure;
- first source/drain regions on opposing sides of the first gate structure, the plurality of first inner spacers being interposed between the first source/drain regions and the first gate structure;
- and
- a plurality of first voids interposed between the first source/drain regions and the first gate structure;
- and
- a second transistor on the substrate, the second transistor comprising:
- a plurality of second nanowire structures over the substrate, the plurality of second nanowire structures comprising a second semiconductor material different than the first semiconductor material, wherein an uppermost surface of an uppermost second nanowire structure of the plurality of second nanowire structures is not level with an uppermost surface of an uppermost first nanowire structure of the plurality of first nanowire structures;
- a second gate structure extending around the plurality of second nanowire structures, the second gate structure having non-planar sidewalls between adjacent ones of the plurality of second nanowire structures;
- a plurality of second inner spacers, each of the plurality of second inner spacers being formed along a corresponding one of the non-planar sidewalls of the second gate structure;
- second source/drain regions on opposing sides of the second gate structure, the plurality of second inner spacers being interposed between the second source/drain regions and the second gate structure;
- and
- a plurality of second voids interposed between the second source/drain regions and the second gate structure.
12 more elements
Dependencies are inferred from the claim text.