Method and structure for forming vertical transistors with various gate lengths
AssigneeInternational Business Machines Corporation
InventorsKangguo CHENG, SHOGO MOCHIZUKI, Choonghyun LEE, Juntao LI
Life of this patent
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Abstract
Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same.
Claims15
A semiconductor structure comprising:
- a first vertical fin field-effect transistor formed on a semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate disposed on the first bottom source/drain junction layer, the first gate having a first gate length;
- and
- a second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate disposed on the second bottom source/drain junction layer, the second gate having a second gate length that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.
An integrated circuit comprising:
- a circuit supporting substrate;
- and
- a semiconductor structure, the semiconductor structure comprising:
- a first vertical fin field-effect transistor formed on a semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate disposed on the first bottom source/drain junction layer, the first gate having a first gate length;
- and
- a second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate disposed on the second bottom source/drain junction layer, the second gate having a second gate length that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.
A semiconductor structure comprising:
- a semiconductor substrate;
- a first vertical fin field-effect transistor formed on the semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate, including a first high-k gate dielectric and a first gate conductor, disposed on the first bottom source/drain junction layer, the first gate having a first gate length vertically along the first vertical fin;
- and
- a second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate, including a second high-k gate dielectric and a second gate conductor, disposed on the second bottom source/drain junction layer, the second gate having a second gate length vertically along the second vertical fin that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.
Dependencies are inferred from the claim text.