Bottom spacer structure for vertical field effect transistor and method of forming same

A semiconductor device, comprising:

• a vertical transistor comprising a source/drain junction region on a semiconductor substrate;
• bottom source/drain regions disposed adjacent the source/drain junction region;
• and
• a bottom spacer pattern comprising first bottom spacers disposed on lateral sides of the source/drain junction region, and second bottom spacers disposed on lateral sides of the first bottom spacers;
• wherein the first and second bottom spacers are formed on top of the bottom source/drain regions;
• and
• wherein top surfaces of first bottom spacers have a planar profile, and top surfaces of the second bottom spacers have a concave shape.

A method for manufacturing a vertical transistor device, comprising:

• forming a fin on a semiconductor substrate;
• forming sacrificial dielectric spacer layers on the fin;
• removing portions of the semiconductor substrate located under the sacrificial dielectric spacer layers and located at sides of the fin;
• forming doped bottom source/drain regions in at least part of an area where the portions of the semiconductor substrate were removed;
• forming doped sacrificial semiconductor layers on the doped bottom source/drain regions;
• diffusing dopants from the doped bottom source/drain regions and the doped sacrificial semiconductor layers into a portion of the semiconductor substrate under the fin;
• removing the doped sacrificial semiconductor layers;
• and
• forming bottom spacers in at least part of an area where the doped sacrificial semiconductor layers were removed.