Method of manufacturing a semiconductor device and a semiconductor device

A method of manufacturing a semiconductor device, comprising:

• forming a first fin structure and a second fin structure, in both which first semiconductor layers and second semiconductor layers are alternately stacked;
• forming a first sacrificial gate structure over the first fin structure and a second sacrificial gate structure over the second fin structure;
• while the second fin structure with the second sacrificial gate structure are protected, etching a source/drain region of the first fin structure, which is not covered by the
• first sacrificial gate structure, thereby forming a first source/drain space;
• laterally etching the first semiconductor layers in the first source/drain space;
• forming a first inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers;
• and
• forming a first source/drain epitaxial layer in the first source/drain space to cover the inner spacer, thereby forming a first structure;
• while the first structure is protected,
• etching the second semiconductor layers in a source/drain region of the second fin structure, which is not covered by the second sacrificial gate structure, thereby forming a second source/drain space;
• laterally etching the second semiconductor layers through the second source/drain space;
• forming a second inner spacer made of a dielectric material on an end of each of the etched second semiconductor layers;
• and
• forming a second source/drain epitaxial layer in the second source/drain space to cover the second inner spacer, thereby forming a second structure.

A semiconductor device, comprising:

• semiconductor wires disposed over a substrate;
• a source/drain epitaxial layer in contact with the semiconductor wires;
• a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires;
• a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region;
• a gate sidewall spacer disposed on a side face of the gate electrode layer;
• and
• insulating spacers each enclosed by adjacent semiconductor wires, the gate dielectric layer and the source/drain region,
• wherein an additional insulating spacer is disposed between an uppermost one of the semiconductor wires and the gate sidewall spacer.