Method of manufacturing a semiconductor device and a semiconductor device

#The disclosure relates to method of manufacturing semiconductor integrated circuits, and more particularly to method of manufacturing semiconductor devices including fin field effect transistors (FinFETs) and/or gate-all-around FETs, and semiconductor devices.

#As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a multi-gate field effect transistor (FET), including a fin FET (Fin FET) and a gate-all-around (GAA) FET. In a Fin FET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween. Because the gate structure surrounds (wraps) the fin on three surfaces, the transistor essentially has three gates controlling the current through the fin or channel region. Unfortunately, the fourth side, the bottom part of the channel is far away from the gate electrode and thus is not under close gate control. In contrast, in a GAA FET, all side surfaces of the channel region are surrounded by the gate electrode, which allows for fuller depletion in the channel region and results in less short-channel effects due to steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). As transistor dimensions are continually scaled down to sub 10-15 nm technology nodes, further improvements of the GAA FET are required.

#The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

#FIGS. 1A-1D show various views of a semiconductor FET device according to embodiments of the present disclosure. FIG. 1A is a perspective view, FIG. 1B is a cross sectional view corresponding to Y1-Y1 of FIG. 1A, FIG. 1C is a cross sectional view corresponding to Y2-Y2 of FIG. 1A, FIG. 1D shows a cross sectional view corresponding to X1-X1 of FIG. 1C.

#FIG. 2 shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.

#It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.

#Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “being made of” may mean either “comprising” or “consisting of.”

#In the present disclosure, a method for fabricating an inner spacer between a metal gate electrode and a source/drain epitaxial layer for a GAA FET and a stacked channel FET are provided. In this disclosure, a source/drain refers to a source and/or a drain. The inner spacer can be formed by the following process. After a dummy gate structure is formed over a stacked fin structure, in which two different semiconductor wires are alternately stacked, a source/drain region of the stacked fin structure is recessed. Then, an insulating (dielectric) layer is formed in the recess and then the formed insulating layer is etched to form inner spacers on ends of the semiconductor wires. Subsequently a source/drain epitaxial layer is formed over the inner spacers. It is noted that in the present disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same.