US 2020/0052082 A1 · Semiconductor Structure for Flash Memory Cells and Method of Making Same

Abstract

An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).

Claims20

Dependent claims

A memory structure comprising:

a plurality of semiconductor portions extending from a substrate, wherein the plurality of semiconductor portions define a plurality of active regions;
a doped layer that continuously spans and is disposed without interruption directly on top surfaces of the plurality of semiconductor portions;
and
a dielectric layer disposed directly on the doped layer, wherein the dielectric layer continuously spans and is disposed without interruption over the top surfaces of the plurality of semiconductor portions.

1 more element

A memory structure comprising:

a first semiconductor extension and a second semiconductor extension from a semiconductor substrate, wherein:
the first semiconductor extension defines a first active region of the memory structure and the second semiconductor extension defines a second active region of the memory structure,
the first semiconductor extension is directly adjacent to the second semiconductor extension, and
the first semiconductor extension and the second semiconductor extension each have a top surface that extends between sidewall surfaces;
a doped layer disposed in the first semiconductor extension, the second semiconductor extension, and a portion of the semiconductor substrate disposed between the first semiconductor extension and the second semiconductor extension, wherein:
the doped layer is disposed along the top surface and the sidewall surfaces of the first semiconductor extension,
the doped layer is disposed along the top surface and the sidewall surfaces of the second semiconductor extension,
the doped layer spans from the first semiconductor extension to the second semiconductor extension without interruption;
and
a dielectric layer disposed on the doped layer, wherein:
the dielectric layer is disposed on the top surface and the sidewall surfaces of the first semiconductor extension,
the dielectric layer is disposed on the top surface and the sidewall surfaces of the second semiconductor extension, and
the dielectric layer spans from the first semiconductor extension to the second semiconductor extension without interruption.

10 more elements

A memory structure comprising:

a first semiconductor extension and a second semiconductor extension from a semiconductor substrate, wherein:
the first semiconductor extension defines a first active region of the memory structure and the second semiconductor extension defines a second active region of the memory structure,
the first semiconductor extension is directly adjacent to the second semiconductor extension, and
the first semiconductor extension and the second semiconductor extension each have a curved top surface;
a doped layer disposed in the first semiconductor extension, the second semiconductor extension, and a portion of the semiconductor substrate disposed between the first semiconductor extension and the second semiconductor extension, wherein:
the doped layer is disposed along the curved top surface of the first semiconductor extension,
the doped layer is disposed along the curved top surface of the second semiconductor extension,
the doped layer spans from the first semiconductor extension to the second semiconductor extension without interruption;
and
a dielectric layer disposed on the doped layer, wherein:
the dielectric layer is disposed on the curved top surface of the first semiconductor extension,
the dielectric layer is disposed on the curved top surface of the second semiconductor extension, and
the dielectric layer spans from the first semiconductor extension to the second semiconductor extension without interruption.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/657,293Filed 18 Oct 2019

Priority

13 Feb 2014

Published

13 Feb 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/6892
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having at least one additional gate other than the…
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10D 64/035
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures

Family

Application14/179,687Division · filed 13 Feb 2014

Application15/617,691Continuation · filed 8 Jun 2017

Application16/657,293Continuation

Application15/617,691Division

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US 2015/0228740 A1Published application

US 2017/0271465 A1Published application

US 9,679,979 B2Related patent

US 2020/0052082 A1This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor Structure for Flash Memory Cells and Method of Making Same

Life of this patent

Semiconductor Structure for Flash Memory Cells and Method of Making Same

Life of this patent

Abstract

Claims20