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US 2020/0052072 A1Published application
High voltage device and manufacturing method thereof
AssigneeRichtek Technology Corporation
InventorTsung-Yi Huang
Life of this patent
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Abstract
A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.
Claims10
A high voltage device comprising:
- a semiconductor layer, which is formed on a substrate, and has a top surface and a bottom surface opposite to the top surface in a vertical direction, wherein the substrate has a first conductivity type;
- an isolation region, which is formed on and in contact with the top surface, wherein the isolation region is for defining a device region;
- a first deep well having the first conductivity type, which is formed in the semiconductor layer;
- a second deep well having a second conductivity type, which is formed below and in contact with the first deep well in the semiconductor layer, the second deep well encompassing a lower boundary of the first deep well;
- a drift well having the second conductivity type, which is formed on and in contact with the first deep well in the semiconductor layer, and overlays an upper boundary of the first deep well, wherein the draft well is below and in contact with the top surface in the vertical direction;
- a first well having the first conductivity type, which is formed on the second deep well outside the device region, and is located below the top surface and in contact with the top surface in the vertical direction, wherein the first well is in contact with the first deep well and electrically connected to the first deep well;
- a second well having the second conductivity type, which is formed on the second deep well outside the device region and outside the first well, and is located below the top surface and in contact with the top surface in the vertical direction, wherein the second well is in contact with and electrically connected to the second deep well;
- a body region having the first conductivity type, which is formed on the second deep well in the drift well within the device region, and is located below the top surface and in contact with the top surface in the vertical direction;
- a body contact having the first conductivity type, which is formed in the body region, and is located below the top surface and in contact with the top surface in the vertical direction, wherein the body contact serves as an electrical contact of the body region;
- a high voltage well having the second conductivity type, which is formed in the second deep well, wherein the high voltage well is not in contact with any of the first deep well, the first well, and the second well;
- a gate, which is formed on the top surface within the device region, wherein part of the first high voltage well is located below and in contact with the gate in the vertical direction, the gate including:
- a dielectric layer, which is formed on and in contact with the top surface, and is in contact with the first high voltage well in the vertical direction;
- a conductive layer, which is formed on and in contact with the dielectric layer, and serves as an electrical contact of the gate;
- and
- a spacer layer, which is formed outside of two sidewalls of the conductive layer, and serves as an electrical insulation layer of the gate;
- and
- a source and a drain having the second conductivity type, which are formed below and in contact with the top surface in the vertical direction within the device region, wherein the source and the drain are located below and outside two sides of the gate respectively, wherein the side of the gate which is closer to the source is a source side and the side of the gate which is closer to the drain is a drain side, and wherein the source is located in the body region, and the drain is located in the drift well outside the drain side;
- wherein an inversion region is formed in the body region between the source and the first high voltage well in a channel direction to serve as an inversion current channel in an ON operation of the high voltage device;
- wherein a drift region is located in the drift well between the drain and the body region in the channel direction, is in contact with the top surface, to serve as a drift current channel in the ON operation of the high voltage device;
- and
- wherein at least part of the high voltage well is located right below all of the drift region.
18 more elements
A manufacturing method of a high voltage device, comprising:
- forming a semiconductor layer on a substrate, semiconductor layer having a top surface and a bottom surface opposite to the top surface in a vertical direction, wherein the substrate has a first conductivity type;
- forming an isolation region on the top surface for defining a device region, wherein the isolation region is in contact with the top surface;
- forming a first deep well having the first conductivity type in the semiconductor layer;
- forming a second deep well having a second conductivity type below and in contact with the first deep well in the semiconductor layer, the second deep well encompassing a lower boundary of the first deep well;
- forming a drift well having the second conductivity type on and in contact with the first deep well in the semiconductor layer, wherein the draft well overlays an upper boundary of the first deep well, and the draft well is below and in contact with the top surface in the vertical direction;
- forming a first well having the first conductivity type on the second deep well outside the device region, wherein the first well is located below the top surface and in contact with the top surface in the vertical direction, and is in contact with the first deep well and electrically connected to the first deep well;
- forming a second well having the second conductivity type on the second deep well outside the device region and outside the first well, wherein the second well is located below the top surface and in contact with the top surface in the vertical direction, and is in contact with and electrically connected to the second deep well;
- forming a body region having the first conductivity type on the second deep well in the drift well within the device region, wherein the body region is located below the top surface and in contact with the top surface in the vertical direction;
- forming a body contact having the first conductivity type in the body region, wherein the body contact is located below the top surface and in contact with the top surface in the vertical direction, and the body contact serves as an electrical contact of the body region;
- forming a high voltage well having the second conductivity type in the second deep well, wherein the high voltage well is not in contact with any of the first deep well, the first well, and the second well;
- forming a gate on the top surface within the device region, wherein part of the drift well is located right below and in contact with the gate in the vertical direction, the gate including:
- a dielectric layer, which is formed on and in contact with the top surface, and is in contact with the first high voltage well in the vertical direction;
- a conductive layer, which is formed on and in contact with the dielectric layer, and serves as an electrical contact of the gate;
- and
- a spacer layer, which is formed outside of two sidewalls of the conductive layer, and serves as an electrical insulation layer of the gate;
- and
- forming a source and a drain having the second conductivity type below and in contact with the top surface in the vertical direction within the device region, wherein the source and the drain are located below and outside two sides of the gate respectively, wherein the side of the gate which is closer to the source is a source side and the side of the gate which is closer to the drain is a drain side, and wherein the source is located in the body region, and the drain is located in the drift well outside the drain side;
- wherein an inversion region is formed in the body region between the source and the first high voltage well in a channel direction to serve as an inversion current channel in an ON operation of the high voltage device;
- wherein a drift region is located in the drift well between the drain and the body region in the channel direction, is in contact with the top surface, to serve as a drift current channel in the ON operation of the high voltage device;
- and
- wherein at least part of the high voltage well is located right below all of the drift region.
18 more elements
Dependencies are inferred from the claim text.