Integrated Memory Comprising Gated Regions Between Charge-Storage Devices and Access Devices

An integrated assembly, comprising:

• a first access transistor and a second access transistor;
• the first access transistor comprising a first gate proximate a first channel region, and the second access transistor comprising a second gate proximate a second channel region;
• the first and second access transistors together comprising three source/drain regions, with one of the three source/drain regions being shared by the first and second access transistors;
• the three source/drain regions being a first source/drain region, a second source/drain region and a third source/drain region, with the first and second source/drain regions being gatedly coupled to one another through the first channel region, and with the second and third source/drain regions being gatedly coupled to one another through the second channel region;
• a digit line coupled with the second source/drain region;
• a first charge-storage device coupled with the first source/drain region through a first interconnect;
• a second charge-storage device coupled with the third source/drain region through a second interconnect;
• a first switch controlling current flow along the first interconnect;
• and
• a second switch controlling current flow along the second interconnect.

An integrated assembly, comprising:

• a first access transistor and a second access transistor;
• the first access transistor comprising a first gate proximate a first channel region, and the second access transistor comprising a second gate proximate a second channel region;
• the first and second access transistors together comprising three source/drain regions, with one of the three source/drain regions being shared by the first and second access transistors;
• the three source/drain regions being a first source/drain region, a second source/drain region and a third source/drain region, with the first and second source/drain regions being gatedly coupled to one another through the first channel region, and with the second and third source/drain regions being gatedly coupled to one another through the second channel region;
• the first channel region extending horizontally between the first and second source/drain regions;
• the second channel region extending horizontally between the second and third source/drain regions;
• a digit line coupled with the second source/drain region;
• a first capacitor coupled with the first source/drain region through a first interconnect;
• the first interconnect comprising a first vertically-extending pillar of a first semiconductor material;
• a second capacitor coupled with the third source/drain region through a second interconnect;
• the second interconnect comprising a second vertically-extending pillar of a second semiconductor material;
• a first protective transistor gating a portion of the first vertically-extending pillar of the first semiconductor material;
• and
• a second protective transistor gating a portion of the second vertically-extending pillar of the second semiconductor material.