Semiconductor device

A semiconductor device comprising:

• a semiconductor base substrate of a first conductive type;
• a first semiconductor region of a second conductive type formed on a surface of a first main surface of the semiconductor base substrate, the first semiconductor region having a plurality of first corner portions and a plurality of first side portions;
• a surface semiconductor region of a second conductive type formed on the surface of the first main surface so as to include a region where the surface semiconductor region overlaps with the first semiconductor region as viewed in a plan view, the surface semiconductor region having a plurality of second corner portions and a plurality of second side portions formed so as to surround the first semiconductor region as viewed in a plan view, and the surface semiconductor region having dopant concentration lower than dopant concentration of the first semiconductor region;
• an insulation film formed on the surface of the first main surface in a range from a region where the first semiconductor region is formed to a region outside the surface semiconductor region as viewed in a plan view;
• a first semiconductor region side electrode formed in a region overlapping with the first semiconductor region as viewed in a plan view;
• and
• a field plate formed in a region overlapping with the surface semiconductor region as viewed in a plan view by way of the insulation film, the field plate having a plurality of field plate corner portions and a plurality of field plate side portions, wherein
• assuming a total length of the surface semiconductor region from an outer edge of the first semiconductor region to an outer edge of the surface semiconductor region as viewed in a plan view of the second corner portion as L1, and assuming a total length of the surface semiconductor region from the outer edge of the first semiconductor region to the outer edge of the surface semiconductor region as viewed in a plan view of the second side portion as L2, and
• assuming a length from the outer edge of the first semiconductor region side electrode to the outer edge of the field plate as viewed in a plan view of the field plate corner portion as FP1, and assuming a length from the outer edge of the first semiconductor region side electrode to the outer edge of the field plate as viewed in a plan view of the field plate side portion as FP2,
• at least one of a condition (1) that a relationship of L1>L2 is established at least at a portion of the surface semiconductor region and a condition (2) that a relationship of FP1>FP2 is established at least at a portion of the field plate is satisfied, and a withstand voltage of the second side portion is lower than a withstand voltage of the second corner portion.