Device Disaggregation For Improved Performance
AssigneeXcelsis Corporation
InventorsJavier A. Delacruz, Don Draper, Jung Ko, Steven L. Teig
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Abstract
The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.
Claims25
A 3D semiconductor device, comprising:
- a first layer in advanced node, the first layer including an active die, active circuitry, and a configurable memory;
- a second layer in legacy node, the second layer including a passive die with wiring, wherein the second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer to connect one or more first points on the active die to one or more second points on the active die;
- and
- a plurality of external interconnects extending through the passive die and adapted to couple the wiring with an external device.
A 3D semiconductor device, comprising:
- a first tier;
- and
- a second tier bonded to the first tier, wherein each of the first tier and the second tier comprises:
- a first layer in advanced node, the first layer including an active die, active circuitry, and a configurable memory;
- and
- a second layer, the second layer including a passive die with wiring, wherein the second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer to connect one or more first points on the active die to one or more second points on the active die.
A field programmable gate array, comprising:
- a first layer in advanced node, the first layer including an active die and active circuitry, the active circuitry comprising a plurality of multiplexers and a plurality of hardcoded logical connections;
- and
- a second layer in legacy node, the second layer including a passive die with wiring, wherein the second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer to connect one or more first points on the active die to one or more second points on the active die.
Dependencies are inferred from the claim text.