Three-dimensional semiconductor device

A three-dimensional semiconductor device, comprising:

• lower gate electrodes on a substrate;
• intermediate gate electrodes on the lower gate electrodes;
• and
• one or more upper gate electrodes on the intermediate gate electrodes,
• wherein the lower gate electrodes include a first lower gate electrode having a first lower pad region, a second lower gate electrode having a second lower pad region, a third lower gate electrode having a third lower pad region, and a fourth lower gate electrode having a fourth lower pad region,
• wherein the first lower pad region, the second lower pad region, the third lower pad region, and the fourth lower pad region are arrayed to have a stepped shape lowered in a first direction,
• wherein the intermediate gate electrodes include a first intermediate gate electrode having a first intermediate pad region, a second intermediate gate electrode having a second intermediate pad region, a third intermediate gate electrode having a third intermediate pad region, and a fourth intermediate gate electrode having a fourth intermediate pad region,
• wherein the first intermediate pad region, the second intermediate pad region, the third intermediate pad region, and the fourth intermediate pad region are arrayed to have a stepped shape lowered in a second direction perpendicular to the first direction,
• wherein a length in the first direction of the second lower pad region is different from a length in the first direction of the third lower pad region,
• wherein a length in the second direction of the second intermediate pad region is different from a length in the second direction of the third intermediate pad region, and
• wherein at least one of the second intermediate pad region and the third intermediate pad region is separated into a pad portion and a dummy portion adjacent to each other in the second direction.

A three-dimensional semiconductor device, comprising:

• lower gate electrodes on a substrate;
• intermediate gate electrodes on the lower gate electrodes;
• and
• upper gate electrodes on the intermediate gate electrodes,
• wherein the intermediate gate electrodes include a first intermediate gate electrode having a first intermediate pad region, a second intermediate gate electrode having a second intermediate pad region, a third intermediate gate electrode having a third intermediate pad region, and a fourth intermediate gate electrode having a fourth intermediate pad region,
• wherein the first intermediate pad region, the second intermediate pad region, the third intermediate pad region, and the fourth intermediate pad region are arrayed to have a stepped shape lowered by the second step portion in the second direction,
• wherein the upper gate electrodes include a first upper gate electrode having a first upper pad region, a second upper gate electrode having a second upper pad region, and a third upper gate electrode having a third upper pad region,
• wherein the first upper pad region, the second upper pad region and the third upper pad region are arrayed to have a stepped shape lowered in a first direction,
• wherein a length of the first direction of the second upper pad region is different from a length in the first direction of the third upper pad region, and
• wherein a length of the second direction of the second intermediate pad region is different from a length in the second direction of the third intermediate pad region,
• wherein at least one of the second intermediate pad region and the third intermediate pad region is separated into a pad portion and a dummy portion adjacent to each other in the second direction.

A three-dimensional semiconductor device, comprising:

• a first main separation structure and a second main separation structure in a memory cell array region and in a connection region of a substrate;
• a first secondary separation structure in the connection region, the first secondary separation structure being between a first main separation structure and a second main separation;
• and
• a single memory block between the first main separation structure and the second main separation structure,
• wherein the single memory block includes gate electrodes stacked in the memory cell array region in a vertical direction perpendicular to a surface of the substrate and extended to the connection region,
• wherein the gate electrodes include pad regions lowered by a first step height in a first direction oriented from the memory cell array region toward the connection region, and lowered a second step height in a second direction oriented from the first main separation structure to the second main separation structure,
• wherein the first step height is greater than the second step height,
• wherein the gate electrodes include a first gate electrode having a first pad region, a second gate electrode having a second pad region, a third gate electrode having a third pad region, and a fourth gate electrode having a fourth pad region,
• wherein the first pad region, the second pad region, the third pad region and the fourth pad region are arrayed to have a stepped shape lowered in the second direction,
• wherein a length in the second direction of the third pad region is less than a length in the second direction of each of the first, second and fourth pad regions.