US 2020/0051995 A1 · THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DIRECT CONTACT DRAIN-SELECT-LEVEL SEMICONDUCTOR CHANNEL PORTIONS AND METHODS OF MAKING THE SAME

Abstract

An alternating stack of insulating layers and word-line-level spacer material layers is formed over a substrate. Memory opening fill structures including a respective memory film, a respective word-line-level semiconductor channel portion, a respective word-line-level dielectric core laterally, and a respective sacrificial dielectric material portion are formed through the alternating stack. Drain-select-level material layers are formed over the alternating stack and the memory opening fill structures. Drain-select-level openings are formed through the drain-select-level material layers and over the memory opening fill structures. The sacrificial dielectric material portions are removed selective to the word-line-level semiconductor channel portions underneath the drain-select-level openings. Drain-select-level semiconductor channel portions are formed directly on a respective one of the word-line-level semiconductor channel portions.

Claims20

Dependent claims

A three-dimensional memory device comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;
a memory opening vertically extending through the alternating stack;
a memory opening fill structure located within the memory opening and comprising a memory film, a word-line-level semiconductor channel portion laterally surrounded by the memory film, and a word-line-level dielectric core laterally surrounded by the word-line-level semiconductor channel portion;
and
a drain-select-level pillar structure overlying the memory opening fill structure and comprising a cylindrical gate electrode, a gate dielectric, and a drain-select-level semiconductor channel portion, wherein an interface between the drain-select-level semiconductor channel portion and the word-line-level semiconductor channel portion is vertically coincident with an interface between the word-line-level semiconductor channel portion and the word-line-level dielectric core.

2 more elements

A method of forming a three-dimensional memory device, comprising:

forming an alternating stack of insulating layers and word-line-level spacer material layers over a substrate, wherein the word-line-level spacer material layers are formed as, or are subsequently replaced with, word-line-level electrically conductive layers;
forming a memory opening through the alternating stack;
forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a memory film, a word-line-level semiconductor channel portion laterally surrounded by the memory film, a word-line-level dielectric core laterally surrounded by the word-line-level semiconductor channel portion, and a sacrificial dielectric material portion;
forming drain-select-level material layers over the alternating stack and the memory opening fill structure;
forming a drain-select-level cavity extending through the drain-select-level material layers and over the memory opening fill structure;
removing the sacrificial dielectric material portion selective to the word-line-level semiconductor channel portions underneath the drain-select-level opening;
and
forming a drain-select-level semiconductor channel portion directly on the word-line-level semiconductor channel portion.

5 more elements

Dependencies are inferred from the claim text.

Three-dimensional memory device containing direct contact drain-select-level semiconductor channel portions and methods of making the same

Life of this patent

Three-dimensional memory device containing direct contact drain-select-level semiconductor channel portions and methods of making the same

Life of this patent

Abstract

Claims20