Memory device improvement

A method of forming a memory device including a plurality of nonvolatile memory cells, the method comprising:

• forming a hole in a stack of alternating insulator layers and memory cell layers to expose an edge surface of each layer in the stack, wherein
• the stack extends from a bottom to a top, and
• the stack includes a plurality of insulator layers and plurality of memory cell layers between the bottom and the top of the stack;
• depositing a first portion of a silicon channel layer, wherein the first portion of the silicon channel layer extends from the bottom of the stack to the top of the stack;
• depositing a second portion of the silicon channel layer, wherein the second portion of the silicon channel layer extends from the bottom of the stack to the top of the stack;
• and
• heating the silicon channel layer to transform the silicon channel layer into a polysilicon channel layer;
• and
• reducing the thickness of the polysilicon channel layer by at least 10% until a target thickness of the polysilicon layer is reached.

A 3-D flash memory device comprising:

• a plurality of memory cells arranged in a stack, wherein the stack is formed over a substrate and each memory cell in the stack is separated from other memory cells in the stack in a vertical direction, each memory cell comprising:
• a charge trap flash layer;
• a polysilicon channel layer doped with a first dopant;
• and
• a gate oxide disposed between the channel layer and the charge trap flash layer.