US 2020/0051989 A1Published application

Semiconductor device

AssigneeToshiba Memory Corporation

InventorsKojiro SHIMIZU, Hanae ISHIHARA, Yumiko MIYANO

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Abstract

A semiconductor device according to an embodiment includes a first contact electrically connected to a first conductive layer with a diameter size smaller than a diameter size of a first support pillar at a region position on an inner side in a radial direction of the first support pillar in a first region and extending to the opposite side of the substrate with respect to the first conductive layer; and a second contact electrically connected to a second conductive layer with a diameter size smaller than a diameter size of a second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate;
a first conductive layer formed in a plate shape, provided above the substrate and extending in parallel with a surface of the substrate so as to spread over first and second regions;
a second conductive layer formed in a plate shape, arranged to be separated at a distance above the first conductive layer so as to have a staircase shape with an end portion of the first conductive layer protruding, the second conductive layer extending in parallel with the first conductive layer so as to spread over the first and second regions;
a first support pillar connected to a lower surface or a side surface of the first conductive layer and extending toward the substrate at a position in the first region and not overlapping with the second conductive layer;
a second support pillar connected to a lower surface or a side surface of the second conductive layer and extending toward the substrate so as to penetrate through the first conductive layer in the first region;
a first contact electrically connected to the first conductive layer with a diameter size smaller than a diameter size of the first support pillar at a region position on an inner side in a radial direction of the first support pillar in the first region and extending to the opposite side of the substrate with respect to the first conductive layer;
a second contact electrically connected to the second conductive layer with a diameter size smaller than a diameter size of the second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer;
a channel body using a semiconductor material and penetrating through the first and second conductive layers in the second region;
and
a memory film including a charge accumulation film and provided between each of the first and second conductive layers and the channel body in the second region.

7 more elements

A semiconductor device comprising:

a substrate;
a first conductive layer formed in a plate shape, provided above the substrate and extending in parallel with a surface of the substrate so as to spread over first and second regions;
a second conductive layer formed in a plate shape, arranged to be separated at a distance above the first conductive layer so as to have a staircase shape with an end portion of the first conductive layer protruding, the second conductive layer extending in parallel with the first conductive layer so as to spread over the first and second regions;
a first conductor film arranged so that a portion thereof is included in the first conductive layer at a position in the first region and not overlapping with the second conductive layer, the first conductor film being connected to a side surface of the first conductive layer, the first conductor film having a film thickness larger than that of the first conductive layer;
a second conductor film arranged so that a portion thereof is included in the second conductive layer in the first region, the second conductor film being connected to a side surface of the second conductive layer, the second conductor film having a film thickness larger than that of the second conductive layer;
a first support pillar arranged with substantially a same diameter size as the first conductor film, the first support pillar being connected to a lower surface of the first conductor film and extending toward the substrate;
a second support pillar arranged with substantially a same diameter size as the second conductor film, the second support pillar being connected to a lower surface of the second conductor film and extending toward the substrate so as to penetrate through the first conductive layer;
a first contact connected to the first conductor film with a diameter size smaller than a diameter size of the first support pillar at a region position on an inner side in a radial direction of the first support pillar in the first region;
a second contact connected to the second conductor film with a diameter size smaller than a diameter size of the second support pillar at a region position on an inner side in a radial direction of the second support pillar in the first region;
a channel body using a semiconductor material and penetrating through the first and second conductive layers in the second region;
and
a memory film including a charge accumulation film and provided between each of the first and second conductive layers and the channel body in the second region.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/291,107Filed 4 Mar 2019
Priority: JP 2018-15182410 Aug 2018
Published: 13 Feb 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10W 72/00
Interconnections or connectors in packages