Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices

An integrated assembly, comprising:

• a first primary access transistor and a second primary access transistor, the first primary access transistor comprising a first gate proximate a first channel region, and the second primary access transistor comprising a second gate proximate a second channel region;
• the first and second primary access transistors together comprising three source/drain regions;
• the three source/drain regions being a first source/drain region, a second source/drain region and a third source/drain region;
• the first and second source/drain regions being gatedly coupled to one another through the first channel region;
• the second and third source/drain regions being gatedly coupled to one another through the second channel region;
• a first charge-storage device coupled with the first source/drain region;
• a second charge-storage device coupled with the third source/drain region;
• a digit line coupled with the second source/drain region through an interconnect;
• and
• a switch controlling current flow along the interconnect.

An integrated assembly, comprising:

• a first primary access transistor and a second primary access transistor, the first primary access transistor comprising a first gate proximate a first channel region, and the second primary access transistor comprising a second gate proximate a second channel region;
• the first and second primary access transistors together comprising three source/drain regions;
• the three source/drain regions being a first source/drain region, a second source/drain region and a third source/drain region;
• the first and second source/drain regions being gatedly coupled to one another through the first channel region;
• the second and third source/drain regions being gatedly coupled to one another through the second channel region;
• the first channel region extending horizontally between the first and second source/drain regions;
• the second channel region extending horizontally between the second and third source/drain regions;
• a first capacitor coupled with the first source/drain region;
• a second capacitor coupled with the third source/drain region;
• a digit line coupled with the second source/drain region through an interconnect;
• the interconnect comprising a vertically-extending pillar of a semiconductor material;
• and
• a secondary access transistor gating a portion of the vertically-extending pillar of the semiconductor material.