Multi-threshold vertical fets with common gates

A semiconductor device comprising:

• a substrate;
• a shallow trench isolation region in the substrate separating at least one n-type doped field effect transistor (nFET) and at least one p-type doped field effect transistor (pFET), wherein the at least one nFET comprises:
• an n-type doped bottom source or drain (source/drain) region, one or more vertically oriented fins formed of silicon extending from the bottom source/drain region, a bottom spacer layer;
• a silicon oxynitride interfacial layer on sidewalls of the one or more vertically oriented fins, a high k dielectric layer overlying the silicon oxynitride interfacial layer, a work function metal on the high k dielectric layer, a top spacer layer and a n-type doped top source/drain region on the top portion of the one or more fins;
• and
• wherein the at least one pFET comprises:
• a p-type doped bottom source/drain region, one or more vertically oriented fins formed of the silicon extending from the bottom source/drain region, a bottom spacer layer;
• a silicon dioxide interfacial layer with aluminum on sidewalls of the one or more vertically oriented fins, a high k dielectric layer overlying the silicon dioxide interfacial layer, a work function metal on the high k dielectric layer, a top spacer layer and a p-type doped top source/drain region on the top portion of the one or more fins;
• wherein the work function metal in the at least one nFET and the at least one pFET is shared.

A semiconductor device comprising:

• an n-type doped field effect transistor (nFET) and a p-type doped field effect transistor (pFET), wherein a shallow trench isolation region filled with a dielectric material electrically isolates the nFET from the pFET;
• one or more vertically oriented silicon fins coupled to n-type doped and p-type doped top and bottom source or drain (source/drain) regions in the nFET and pFET, respectively, wherein the nFET and pFET share a common work function metal formed on a high k dielectric;
• a silicon oxynitride interfacial layer on sidewalls of the one or more vertically oriented silicon fins in the nFET, and
• a silicon oxide interfacial layer with aluminum on sidewalls of the one or more vertically oriented silicon fins in the pFET.