Isolated Wells for Resistor Devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Lung Tung, Min-Chang Liang, Fang Chen
Life of this patent
Estimating the term…
Abstract
A method performed by a computing system includes receiving a circuit design, the circuit design comprising a plurality of non-contiguous doped wells within a substrate and a plurality of resistor elements positioned above the plurality of non-contiguous doped wells such that each of the resistor elements is positioned above a different one of the plurality of non-contiguous doped wells and simulating performance of the circuit design with a first voltage applied to a first one of the plurality of resistor elements and a second voltage simultaneously applied to a second one of the plurality of resistor elements, the second voltage being different than the first voltage.
Claims20
A method performed by a computing system, the method comprising:
- receiving a circuit design, the circuit design comprising a plurality of non-contiguous doped wells within a substrate and a plurality of resistor elements positioned above the plurality of non-contiguous doped wells such that each of the resistor elements is positioned above a different one of the plurality of non-contiguous doped wells;
- and
- simulating performance of the circuit design with a first voltage applied to a first one of the plurality of resistor elements and a second voltage simultaneously applied to a second one of the plurality of resistor elements, the second voltage being different than the first voltage.
The method of claim 8, further comprising, adjusting the circuit design based on the simulating.
A method performed by a computing system, the method comprising:
- receiving a circuit design, the circuit design comprising a plurality of non-contiguous doped wells within a substrate and a plurality of resistor elements positioned above the plurality of non-contiguous doped wells such that each of the resistor elements is positioned above a different one of the plurality of non-contiguous doped wells, each of the plurality of resistor elements extending longitudinally beyond the non-contiguous doped wells;
- and
- simulating performance of the circuit design with a first voltage applied to a first one of the plurality of resistor elements and a second voltage simultaneously applied to a second one of the plurality of resistor elements, the second voltage being different than the first voltage.
A system comprising:
- a processor;
- and
- a memory comprising machine readable instructions that when executed by the processor, cause the system to:
- receive a circuit design, the circuit design comprising a plurality of non-contiguous doped wells within a substrate and a plurality of resistor elements positioned above the plurality of non-contiguous doped wells such that each of the resistor elements is positioned above a different one of the plurality of non-contiguous doped wells;
- and
- simulate performance of the circuit design with a first voltage applied to a first one of the plurality of resistor elements and a second voltage simultaneously applied to a second one of the plurality of resistor elements, the second voltage being different than the first voltage.
Dependencies are inferred from the claim text.