Die stack with reduced warpage

A microelectronic device comprising:

• a polymer layer;
• a semiconductor spaced from the polymer layer;
• a signal distribution layer disposed between the polymer layer and the semiconductor, the signal distribution layer including a first coefficient of thermal expansion;
• a matching layer adjacent the semiconductor opposite the signal distribution layer, the matching layer including a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

A microelectronic device package, comprising:

• a substrate including a plurality of conductive elements;
• a plurality of NAND modules oriented in a stacked configuration relative to the substrate, each NAND module electrically connected to one of the plurality of conductive elements, each NAND module comprising:
• a polymer layer including a first coefficient of thermal expansion;
• a semiconductor;
• a signal distribution layer disposed between the semiconductor and the polymer layer, the signal distribution layer including a second coefficient of thermal expansion;
• and
• a matching layer adjacent the semiconductor and opposite the signal distribution layer;
• the matching layer including a third coefficient of thermal expansion that is about the same as one or more of the first coefficient of thermal expansion and the second coefficient of thermal expansion;
• and
• an encapsulation layer enclosing the plurality of NAND modules.

A method of forming a microelectronic device, comprising:

• providing a wafer comprising a polymer layer including a first coefficient of thermal expansion, a distribution layer including a second coefficient of thermal expansion, and a semiconductor;
• coating the semiconductor with a material having a third coefficient of thermal expansion that is about the same as one or more of the first coefficient of thermal expansion and the second coefficient of thermal expansion;
• and
• curing the material.