Semiconductor device and method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorsTomohiko AIKA, Takayuki IGARASHI, Takehiro OCHI
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Abstract
Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.
Claims17
A semiconductor device, comprising:
- semiconductor substrates;
- an element isolation region formed on the semiconductor substrate;
- a gate electrode for MISFET formed on the semiconductor substrate with a gate insulating film interposed between the semiconductor substrate;
- a first sidewall spacer formed on a side surface of the gate electrode;
- a silicon pattern for a fuse element formed on the element isolation region;
- a first metal silicide layer formed on the upper surface and the side surface of the silicon pattern;
- and
- a second metal silicide layer formed on the upper surface of the gate electrode,
- wherein a first height from a lower surface of the silicon pattern to a lower end of the first metal silicide layer in a cross section perpendicular to an extension direction of the silicon pattern is lower than a second height from a lower surface of the gate electrode to a lower end of the second metal silicide layer in a cross section perpendicular to a gate width direction of the gate electrode.
A method of manufacturing a semiconductor device comprising the step of:
- (a) preparing the semiconductor substrate;
- (b) forming an element isolation region made of an insulator on the semiconductor substrate;
- (c) after the step (b), forming a gate electrode for MISFET on the semiconductor substrate with a gate insulating film interposed therebetween;
- and
- forming a silicon pattern for a fuse element on the element isolation region;
- (d) after the step (c) forming a first sidewall spacer on a side surface of the gate electrode;
- and
- forming a second sidewall spacer on a side surface of the silicon pattern;
- (e) after the step (d) forming semiconductor region for source or drain of the MISFET on the semiconductor substrates by ion implantation;
- (f) after the step (e) forming a mask layer covering the gate electrode and the first sidewall spacer and exposing the silicon pattern and the second sidewall spacer;
- (g) after the step (f), etching the second sidewall spacer;
- (h) after the step (g), removing the mask layer;
- (i) after the step (h) forming a metal film on the semiconductor substrate so as to cover the gate electrode, the first sidewall spacer, and the silicon pattern;
- (j) after the step (i) reacting the metal film with the semiconductor region, the gate electrode, and the silicon pattern by heat treatment;
- and
- (k) after the step (j) removing the metal film that has not reacted in the step (j),
- wherein, in the step (j), the silicon pattern and the metal film react with each other to form a first metal silicide layer on the upper surface and the side surface of the silicon pattern, the gate electrode and the metal film react with each other to form a second metal silicide layer on the upper surface of the gate electrode, and the semiconductor region and the metal film react with each other to form a third metal silicide layer on the upper surface of the semiconductor region.
Dependencies are inferred from the claim text.