Semiconductor device and manufacturing method thereof

A manufacturing method of a semiconductor device having a first capacitive element and a second capacitive element, comprising the steps of:

• (a) providing a substrate having a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a semiconductor layer formed over the first insulating layer;
• (b) forming a first active region and a second active region that are surrounded in plan view by a second insulating layer that penetrates through the semiconductor layer and the first insulating layer to reach the semiconductor substrate;
• (c) forming a semiconductor region in the semiconductor substrate so as to include the first active region and the second active region;
• (d) removing the semiconductor layer and the first insulating layer in the second active region;
• and
• (e) in the first active region, forming a first conductor layer over the semiconductor layer via a third insulating layer,
• wherein the first capacitive element is comprised of the semiconductor layer, the third insulating layer, and the first conductor layer,
• wherein the second capacitive element is comprised of the semiconductor region, the first insulating layer, and the semiconductor layer, and
• wherein each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

A manufacturing method of a semiconductor device comprising the steps of:

• (a) providing a substrate having a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a semiconductor layer formed over the first insulating layer, and further having, in a main surface of the semiconductor substrate, a first region where a first capacitive element and a second capacitive element are to be formed, a second region where a first MISFET is to be formed, and a third region where a second MISFET is to be formed;
• (b) removing the semiconductor layer and the first insulating layer in the third region;
• (c) forming a semiconductor region in the semiconductor substrate in the first region;
• (d) forming a second insulating layer over the semiconductor layer in the first region and over the semiconductor substrate in the third region;
• (e) forming a third insulating layer having a smaller thickness than the second insulating layer over the semiconductor layer in the second region;
• (f) forming a first conductor layer over the second insulating layer in the first region, a second conductor layer over the third insulating layer in the second region, and a third conductor layer over the second insulating layer in the third region, respectively;
• (g) in the second region, forming a second semiconductor region in the semiconductor layers at both ends of the second conductor layer;
• and
• (h) in the third region, forming a third semiconductor region in the semiconductor substrate at both ends of the third conductor layer,
• wherein in the first region, the first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the first conductor layer,
• wherein in the first region, the second capacitive element is comprised of the semiconductor region, the first insulating layer, and the semiconductor layer, and
• wherein each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.