Post-grind die backside power delivery
AssigneeIntel Corporation
InventorsMin-Tih Ted Lai, Tyler Leuten, Florence R. Pon
Life of this patent
Estimating the term…
Abstract
Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
Claims25
A method of manufacturing a die, the method comprising:
- receiving a material layer having top side and a backside;
- forming a plurality of holes in the material layer;
- forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes;
- and
- forming a plurality of metal channels on the backside of the material layer, each of the plurality of metal channels electrically connecting a corresponding subset of the plurality of vias.
A method of manufacturing a microelectronics package, the method comprising:
- forming a substrate;
- forming a first die and a second die, wherein forming each of the first die and the second die comprises:
- plurality of holes in a material layer having a top side and a backside,
- forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes, and
- forming a plurality of metal channels on the backside of the material layer, each of the plurality of metal channels electrically connecting a corresponding subset of the plurality of vias;
- embedding, at least partially, the first die into the substrate;
- stacking the second die on top of the first die;
- and
- electrically coupling the first die to the second die via a plurality of pad connections.
A method of manufacturing a die, the method comprising:
- receiving a material layer having top side and a backside;
- forming a plurality of holes in the material layer;
- forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes;
- forming a first metal layer on the backside of the material layer, the metal layer electrically connecting a corresponding first subset of the plurality of vias;
- forming a passive layer adjacent the first metal layer;
- and
- forming a second metal layer on the passive layer, the second metal layer electrically connecting a corresponding second subset of the plurality of vias.
A method of manufacturing a microelectronics package, the method comprising:
- forming a substrate;
- forming a first die and a second die, wherein forming each of the first die and the second die comprises:
- plurality of holes in a material layer having a top side and a backside,
- forming a plurality of vias, each of the plurality of vias corresponding to one of the plurality of holes,
- forming a first metal layer on the backside of the material layer, the first metal layer electrically connecting a corresponding first subset of the plurality of vias,
- forming a passive layer adjacent the first metal layer, and
- forming a second metal layer on a side of the passive layer, the second metal layer electrically connecting a corresponding second subset of the plurality of vias;
- embedding, at least partially, the first die into the substrate;
- stacking the second die on top of the first die;
- and
- electrically coupling the first die to the second die via a plurality of pad connections.
Dependencies are inferred from the claim text.