Boundary protection for cmos multi-threshold voltage devices
AssigneeInternational Business Machines Corporation
InventorsJing Guo, Ekmini A. De Silva, Nicolas Loubet, Indira Seshadri, Nelson Felix
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Abstract
Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
Claims20
A method for protecting a boundary between an n-type doped field effect transistor (nFET) region and a p-type doped field effect transistor (pFET) region in a semiconductor device, the method comprising:
- conformally depositing a work function metal over channel structures provided in the nFET region and the pFET region;
- depositing and patterning an organic planarizing layer to block the channel structures in a selected one of the nFET region and the pFET region;
- removing a nominal thickness of the work function metal from the other one of the nFET and pFET region, wherein removing the nominal thickness laterally removes a portion of the work function metal to form an undercut in the organic planarizing layer;
- reflowing the organic planarizing layer to fill the undercut and completely cover the work function metal underlying the organic planarizing layer;
- and
- fully removing a remaining portion of work function metal from the other one of the nFET region and the pFET region, wherein fully removing the remaining work function metal does not remove any additional amount of the work function metal underlying the organic planarizing layer.
A method for protecting a boundary between an nFET region and a pFET region in a semiconductor device, the method comprising:
- depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region;
- processing structures in the other one of the nFET region and the pFET region to form an undercut in the organic planarizing layer;
- and
- reflowing the organic planarizing layer to fill the undercut, wherein reflowing comprises heating the organic planarizing layer to temperature greater than a glass transition temperature of the organic planarizing layer.
A method for protecting a boundary between an nFET region and a pFET region in a semiconductor device, the method comprising:
- depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region;
- processing structures in the other one of the nFET region and the pFET region to form an undercut in the organic planarizing layer;
- reflowing the organic planarizing layer to fill the undercut, wherein reflowing comprises decrosslinking the organic planarizing layer by exposing the organic planarizing layer to activating radiation and/or thermal radiation in an amount effective to cause the decrosslinking and reflow of the organic planarizing layer.
Dependencies are inferred from the claim text.