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US 2020/0051857 A1Published application
Method of Semiconductor Integrated Circuit Fabrication
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
Claims20
A device comprising:
- a metal layer disposed over a substrate, the metal layer including a first portion and a second portion, wherein the first portion includes a top surface at a level within the device and the second portion includes a top surface at the same level within the device, wherein the first portion is spaced apart from the second portion of the metal layer;
- a catalyst layer disposed directly on the top surface the first portion of the metal layer;
- a plurality of carbon nanotubes (CNTs) extending from the catalyst layer;
- and
- a hard mask layer disposed directly on the top surface of the second portion of the metal layer.
2 more elements
A device comprising:
- a first conductive feature and a second conductive feature disposed over a substrate, the first conductive feature having a first sidewall and an opposing second sidewall such that a first width of the first conductive feature is measured from the first sidewall to the opposing second sidewall of the first conductive feature;
- a catalyst layer disposed over the first conductive feature without being disposed over the second conductive feature;
- and
- a plurality of carbon nanotubes (CNTs) extending from the catalyst layer, the plurality of CNTs have the same first width as the first conductive feature.
1 more element
A device comprising:
- a conductive layer disposed over a substrate, wherein the conductive layer includes a first portion and a second portion that extend to the same level over the substrate, the first portion electrically coupled to a first set of components and the second portion electrically coupled to a second set of components, the second set of components being different than the first set of components;
- a catalyst layer extending from the first portion of the conductive layer;
- a plurality of carbon nanotubes (CNTs) extending from the catalyst layer;
- a hard mask layer extending from the second portion of the conductive layer;
- and
- a dielectric layer extending from the first portion of the conductive layer to the second portion of the conductive layer.
3 more elements
Dependencies are inferred from the claim text.