Contact Plug without Seam Hole and Methods of Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Yuan Ting, Jyu-Horng Shieh
Life of this patent
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Abstract
A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.
Claims21
-20. (canceled)
A device comprising:
- a semiconductor substrate;
- a transistor comprising:
- a gate stack;
- a source/drain region on a side of the gate stack;
- an inter-layer dielectric, wherein the gate stack is in the inter-layer dielectric, and wherein the inter-layer dielectric comprises an air gap therein;
- a source/drain contact plug over and electrically coupling to the source/drain region, wherein the source/drain contact plug is in the inter-layer dielectric;
- and
- a dielectric layer over the inter-layer dielectric, wherein a bottom surface of the dielectric layer is exposed to the air gap.
A device comprising:
- a gate stack;
- a gate spacer on a sidewall of the gate stack;
- a source/drain region on a side of the gate stack;
- a gate contact plug over and electrically connecting to the gate stack;
- a source/drain contact plug over and electrically connected to the source/drain region, wherein entireties of the gate contact plug and the source/drain contact plug are formed of a same material;
- and
- an inter-layer dielectric, wherein the gate contact plug and the source/drain contact plug are embedded in the inter-layer dielectric.
A device comprising:
- a semiconductor substrate;
- a gate dielectric over the semiconductor substrate;
- a gate electrode over the gate dielectric;
- a gate silicide region over the gate electrode;
- a gate spacer on sidewalls of the gate dielectric, the gate electrode, and the gate silicide region;
- a gate contact plug over and contacting the gate silicide region;
- an inter-layer dielectric extending from top of the gate contact plug to bottom of the gate spacer;
- and
- a void in the inter-layer dielectric, wherein the void extends to a top surface of the inter-layer dielectric.
Dependencies are inferred from the claim text.