Impedance matching network and method

A method of matching an impedance comprising:

• coupling an RF input of a matching network to an RF source;
• coupling an RF output of the matching network to a plasma chamber, wherein the matching network comprises at least one EVC, each EVC comprising discrete capacitors each having a corresponding switching circuit, wherein each switching circuit for a corresponding discrete capacitor comprises:
• a first diode operably coupled to the discrete capacitor;
• a capacitor coupled in series with the first diode;
• and
• a second diode operably coupled to the discrete capacitor, the second diode parallel to the first diode and the capacitor coupled in series;
• and
• matching an impedance by at least one of the switching circuits of the at least one EVC switching in or out its corresponding discrete capacitor to alter a total capacitance of the EVC.

A semiconductor processing tool comprising:

• a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate;
• and
• an impedance matching network operably coupled to the plasma chamber, the matching network comprising:
• a RF input operably coupled to an RF source;
• an RF output operably coupled to the plasma chamber;
• and
• at least one EVC, each EVC comprising discrete capacitors each having a corresponding switching circuit, each switching circuit configured to switch in and out its corresponding discrete capacitor to alter a total capacitance of the EVC;
• wherein each switching circuit comprises:
• a first diode operably coupled to the discrete capacitor;
• a capacitor coupled in series with the first diode;
• and
• a second diode operably coupled to the discrete capacitor, the second diode parallel to the first diode and the capacitor coupled in series.

A method of fabricating a semiconductor, the method comprising:

• placing a substrate in a plasma chamber configured to deposit a material layer on the substrate or etch a material layer from the substrate;
• energizing plasma within the plasma chamber by coupling RF power from an RF source to the plasma chamber to perform the deposition or etching;
• and
• while energizing the plasma, carrying out an impedance match by an impedance matching network coupled between the plasma chamber and the RF source, the matching network comprising:
• at least one EVC, each EVC comprising discrete capacitors each having a corresponding switching circuit, each switching circuit configured to switch in and out its corresponding discrete capacitor to alter a total capacitance of the EVC;
• wherein each switching circuit comprises:
• a first diode operably coupled to the discrete capacitor;
• a capacitor coupled in series with the first diode;
• and
• a second diode operably coupled to the discrete capacitor, the second diode parallel to the first diode and the capacitor coupled in series.