Access schemes for access line faults in a memory device
AssigneeMicron Technology, Inc.
InventorYasushi Matsubara
Life of this patent
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Abstract
Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.
Claims23
A method, comprising:
- receiving a signal indicating whether an access operation is being performed with at least one word line of a section of a memory device that includes a first word line;
- isolating, based at least in part on receiving the signal, the first word line of the section of the memory device from a voltage source during a first portion of a period when the first word line is deselected;
- determining that an access operation associated with a second word line of the section of the memory device is performed during a second portion of the period when the first word line is deselected;
- and
- coupling the first word line with the voltage source during the second portion of the period when the first word line is deselected based at least in part on determining that the access operation associated with the second word line is performed during the second portion of the period when the first word line is deselected.
An apparatus comprising:
- memory cells;
- digit lines;
- a first word line and a second word line each configured to selectively couple the memory cells with the digit lines;
- and
- a controller operable to:
- receiving a signal indicating whether an access operation is being performed with at least one word line of a section of a memory device that includes the first word line;
- isolate the first word line from a voltage source during a first period of a standby state of the first word line, the standby state corresponding to a state in which the memory cells are not accessed using the first word line;
- determine that an access operation associated with the second word line is being performed during a second period of the standby state, wherein the second word line is included in the section of the memory device;
- and
- couple the first word line with the voltage source during the second period of the standby state for the first word line based at least in part on determining that the access operation associated with the second word line is being performed.
An apparatus comprising:
- memory cells;
- a set of access lines comprising a first access line configured to activate cell selection components associated with a set of the memory cells;
- and
- a circuit configured to:
- identify that the first access line is associated with a fault;
- and
- receive a signal indicating whether an access operation is being performed with at least one of the set of access lines included in a section of a memory device that includes the first access line;
- and
- couple the first access line with a voltage source based at least in part on the signal indicating that the access operation is being performed;
- or
- isolate the first access line from the voltage source based at least in part on the signal indicating that the access operation is not being performed.
Dependencies are inferred from the claim text.