Shift register unit, shift register circuit and display device

A system, comprising:

• a shift register circuit comprising a plurality of shift register units, wherein each of the shift register units comprises:
• a detection input circuit coupled to a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first input terminal, a first power signal terminal, a pull-up node, and a first node, and configured to transmit a signal from the third clock signal terminal to the pull-up node in response to a signal from the first clock signal terminal and a signal from the second clock signal terminal;
• a display input circuit coupled to a second input terminal, the pull-up node, and a second power signal terminal, and configured to transmit a signal from the second power signal terminal to the pull-up node in response to a signal from the second input terminal;
• an inverter circuit coupled to a third power signal terminal, the pull-up node, a pull-down node, the first node, and the first power signal terminal, and configured to transmit a signal from the third power signal terminal to the pull-down node in response to the signal from the third power signal terminal, transmit a signal from the first power signal terminal to the pull-down node in response to a signal from the pull-up node, and transmit the signal from the first power signal terminal to the pull-up node in response to a signal from the pull-down node;
• a pull-down circuit coupled to the pull-down node, the first power signal terminal, a fourth power signal terminal, an output terminal, and a first signal output terminal, and configured to, in response to the signal from the pull-down node, transmit the signal from the first power signal terminal to the output terminal and transmit a signal from the fourth power signal terminal to the first signal output terminal;
• a reset circuit coupled to the second clock signal terminal, the pull-up node, the first power signal terminal, a third input terminal, and the first node, and configured to transmit the signal from the first power signal terminal to the pull-up node in response to the signal from the second clock signal terminal and transmit the signal from the first power signal terminal to the pull-up node in response to a signal from the third input terminal;
• and
• a first output circuit, coupled to a fourth clock signal terminal, the pull-up node, the output terminal and the first signal output terminal and configured to transmit a signal from the fourth clock signal terminal to the output terminal and the first signal output terminal in response to the signal from the pull-up node, wherein:
• the first clock signal terminal of the shift register unit in an Nth row receives a first clock signal, and the first clock signal terminal of the shift register unit in an (N+1)th row receives the first clock signal;
• the second clock signal terminal of the shift register unit in the Nth row receives a second clock signal, and the third clock signal terminal of the shift register unit in the Nth row receives a third clock signal;
• the third clock signal terminal of the shift register unit in the (N+1)th row receives the second clock signal, and the second clock signal terminal of the shift register unit in the (N+1)th row receives the third clock signal;
• the output terminal of the shift register unit in the Nth row is respectively coupled to the first input terminal of the shift register unit in the (N+1)th row and the second input terminal of the shift register unit in the (N+2)th row;
• the output terminal of the shift register unit in the (N+1)th row is respectively coupled to the first input terminal of the shift register unit in the (N+2)th row and the second input terminal of the shift register unit in the (N+3)th row;
• the third input terminal of the shift register unit in the Nth row is coupled to the output terminal of the shift register unit in the (N+3)th row;
• and
• the first input terminal and the second input terminal of the shift register unit in a first row and the second input terminal of the shift register unit in a second row receive a drive signal, wherein the N is one of an odd number and an even number.

A display device, comprising:

• a shift register unit, wherein the shift register unit comprises:
• a detection input circuit coupled to a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first input terminal, a first power signal terminal, a pull-up node, and a first node, and configured to transmit a signal from the third clock signal terminal to the pull-up node in response to a signal from the first clock signal terminal and a signal from the second clock signal terminal;
• a display input circuit coupled to a second input terminal, the pull-up node, and a second power signal terminal, and configured to transmit a signal from the second power signal terminal to the pull-up node in response to a signal from the second input terminal;
• an inverter circuit coupled to a third power signal terminal, the pull-up node, a pull-down node, the first node, and the first power signal terminal, and configured to transmit a signal from the third power signal terminal to the pull-down node in response to the signal from the third power signal terminal, transmit a signal from the first power signal terminal to the pull-down node in response to a signal from the pull-up node, and transmit the signal from the first power signal terminal to the pull-up node in response to a signal from the pull-down node;
• a pull-down circuit coupled to the pull-down node, the first power signal terminal, a fourth power signal terminal, an output terminal, and a first signal output terminal, and configured to, in response to the signal from the pull-down node, transmit the signal from the first power signal terminal to the output terminal and transmit a signal from the fourth power signal terminal to the first signal output terminal;
• a reset circuit coupled to the second clock signal terminal, the pull-up node, the first power signal terminal, a third input terminal, and the first node, and configured to transmit the signal from the first power signal terminal to the pull-up node in response to the signal from the second clock signal terminal and transmit the signal from the first power signal terminal to the pull-up node in response to a signal from the third input terminal;
• and
• a first output circuit coupled to a fourth clock signal terminal, the pull- up node, the output terminal, and the first signal output terminal, and configured to transmit a signal from the fourth clock signal terminal to the output terminal and the first signal output terminal in response to the signal from the pull-up node.