Shift register, method for driving the same, gate drive circuitry and display apparatus

A gate drive circuitry, comprising a plurality of cascaded shift registers, a first initial signal terminal and a second initial signal terminal,

• wherein each of the plurality of shift registers comprises:
• an input circuit, an output circuit and a pull-up node control circuit,
• wherein the input circuit is connected to a signal input terminal, a pull-up node and a first control terminal and is configured to provide a signal of the signal input terminal to the pull-up node under the control of the first control terminal, the output circuit is connected to the pull-up node, a first clock signal terminal and a signal output terminal and is configured to output a signal of the first clock signal terminal to the signal output terminal under the control of the pull-up node, and the pull-up node control circuit is connected to the pull-up node, a second clock signal terminal, a third clock signal terminal and a first voltage terminal and is configured to provide a signal of the first voltage terminal to the pull-up node under the control of the second clock signal terminal and the third clock signal terminal;
• a first stage of the shift registers comprises a first control terminal and a signal input terminal both connected to the first initial signal terminal, a reset signal terminal connected to a signal output terminal of a second stage of the shift registers, and a second control terminal connected to a pull-up node of a third stage of the shift registers,
• the second stage of the shift registers comprises a first control terminal connected to the second initial signal terminal, a signal input terminal connected to a signal output terminal of the first stage of the shift registers, a reset signal terminal connected to a signal output terminal of the third stage of the shift registers, and a second control terminal connected to a pull-up node of a fourth stage of the shift registers, and
• an (N+2)th stage of the shift registers comprises a first control terminal connected to a pull-up node of an Nth stage of the shift registers, a signal input terminal connected to a signal output terminal of an (N+1)th stage of the shift registers, a reset signal terminal connected to a signal output terminal of an (N+3)th stage of the shift registers, and a second control terminal connected to a pull-up node of an (N+4)th stage of the shift registers, where N is a positive integer.