Power switch circuit and method providing power supply to memory device

A power switch circuit comprising:

• a first level shifter configured to perform operations to open and close a first switching element that is configured to receive a supply voltage provided from a voltage supply pad;
• a second level shifter configured to perform operations to open and close a second switching element connected to the first switching element and a one-time programmable (OTP) memory cell array, and configured to determine whether to provide the supply voltage to the OTP memory cell array;
• a third level shifter configured to perform operations to open and close a third switching element connected to the OTP memory cell array, and configured to determine whether to provide a power voltage to the OTP memory cell array;
• and
• an Electro-Static Discharge (ESD) protection circuit configured to turn off the first switching element in response to an ESD voltage provided from the voltage supply pad.

A method comprising:

• receiving a programming voltage through a first switching element connected between an external voltage source and a voltage supply pad in response to a program operation;
• applying the programming voltage to a memory cell array through a second switching element;
• reading the programmed data by applying an internally generated power voltage to the memory cell array through a third switching element in response to a read operation;
• and
• turning off the first switching element when an Electro-Static Discharge (ESD) voltage is flowed to the voltage supply pad.