Memory arrangement and method for operating or testing a memory arrangement
AssigneeAms AG
InventorsGregor SCHATZBERGER, Friedrich Peter LEISENBERGER, Peter SARSON
Life of this patent
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Abstract
A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.
Claims15
A memory arrangement, comprising
- a non-volatile memory plane,
- a replacement plane,
- an address select block, and
- a counter arrangement having at least one counter,
- wherein the at least one counter is configured to be incremented at a write cycle of the memory arrangement and
- wherein the address select block is configured to switch from the non-volatile memory plane to the replacement plane, if a counter value of the at least one counter is higher than a predetermined limit.
A method for operating a memory arrangement, comprising
- storing information in a non-volatile memory plane in a write cycle,
- counting the write cycle by at least one counter of a counter arrangement and
- storing further information in a replacement plane, if a counter value of the at least one counter is higher than a predetermined limit, and in the non-volatile memory plane, if the counter value of the at least one counter is equal or lower than the predetermined limit.
The method for testing a memory arrangement, comprising
- determining an address of a bit cell by an erase test and/or a program test of the bit cells of a non-volatile memory plane of the memory arrangement,
- storing the address of the bit cell as a preselected bit cell in an address replacement plane of the memory arrangement, and
- storing an address of a replacement bit cell of a replacement plane of the memory arrangement in the address replacement plane.
Dependencies are inferred from the claim text.