Bias scheme for word programming in non-volatile memory and inhibit disturb reduction

A memory device, comprising:

• a non-volatile memory array divided into a flash memory portion and an electrically erasable programmable read-only memory portion, the non-volatile memory array including memory cells arranged in rows and columns, wherein each memory cell includes:
• a memory transistor including an implant in source and drain regions, wherein the implant extends at least partly under an oxide-nitride-oxide stack of the memory transistor;
• and
• a select transistor including a shared source region, wherein the shared source region is shared between two adjacent memory cells of a same row of the non-volatile memory array;
• wherein the flash memory portion and the electrically erasable programmable read-only memory portion are disposed within one single semiconductor die.