US 2020/0051641 A1Published application

Semiconductor memory device

AssigneeToshiba Memory Corporation

InventorsHiroshi Sukegawa, lkuo Magaki, Tokumasa Hara, Shirou Fujita

Life of this patent

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Abstract

A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Claims14

Dependent claims

A method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including:
first to n-th (n is an integer of 2 or more) strings, each of the first to n-th strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;
a bit line electrically connected to the first to n-th strings;
first to n-th select gate lines, the k-th (k is an integer that satisfies 1≤k≤n) select gate line electrically connected to a gate of the select transistor of the k-th string;
a first word line electrically connected to gates of the first memory cells of the first to n-th strings;
a second word line electrically connected to gates of the second memory cells of the first to n-th strings,
a third word line electrically connected to gates of the third memory cells of the first to n-th strings;
and
a fourth word line electrically connected to gates of the fourth memory cells of the first to n-th strings, the method comprising:
performing first to n-th write processes;
and
performing (n+1)-th to 2n-th write processes after performing the first to n-th write processes, wherein
the (i+1)-th (i is an integer that satisfies 1≤i≤(n−1)) write process is performed after performing the i-th write process,
the (j+1)-th (j is an integer that satisfies (n+1)≤j≤(2n−1)) write process is performed after performing the j-th write process,
the k-th write process includes writing data in the first memory cell of the k-th string and writing data in the second memory cell of the k-th string after the writing in the first memory cell of the k-th string, and
the (n+k)-th write process includes writing data in the third memory cell of the k-th string and writing data in the fourth memory cell of the k-th string after the writing in the third memory cell of the k-th string.

13 more elements

A method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including:
first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;
a bit line electrically connected to the first and the second strings;
a first select gate line electrically connected to a gate of the select transistor of the first string;
a second select gate line electrically connected to a gate of the select transistor of the second string;
a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string;
a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string,
a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string;
and
a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string, the method comprising:
applying a voltage to the first word line for writing data in the first memory cell of the first string;
applying a voltage to the second word line for writing data in the second memory cell of the first string after the applying of a voltage to the first word line for the write in the first memory cell of the first string;
applying a voltage to the first word line for writing data in the first memory cell of the second string after the applying of a voltage to the second word line for the write in the second memory cell of the first string;
applying a voltage to the second word line for writing data in the second memory cell of the second string after the applying of a voltage to the first word line for the write in the first memory cell of the second string;
applying a voltage to the third word line for writing data in the third memory cell of the first string after the applying of a voltage to the second word line for the write in the second memory cell of the second string;
applying a voltage to the fourth word line for writing data in the fourth memory cell of the first string after the applying of a voltage to the third word line for the write in the third memory cell of the first string;
applying a voltage to the third word line for writing data in the third memory cell of the second string after the applying of a voltage to the fourth word line for the writing data in the fourth memory cell of the first string;
and
applying a voltage to the fourth word line for writing data in the fourth memory cell of the second string after the applying of a voltage to the third word line for the write in the third memory cell of the second string.

16 more elements

Facts

Application: 16/656,673Filed 18 Oct 2019
Priority: 2 Aug 2013
Published: 13 Feb 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G06F 3/064
Organizing or formatting or addressing of data: management of blocks
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…

Family

Application61/861,456Us provisional application · filed 2 Aug 2013
Application14/200,641Continuation · filed 7 Mar 2014
Application15/230,857Continuation · filed 8 Aug 2016
Application16/045,956Continuation · filed 26 Jul 2018
Application16/656,673Continuation
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From the US filing history. Foreign family members aren’t listed.