Semiconductor memory device

A semiconductor memory device having a first read mode and a second read mode, comprising:

• a first memory cell and a second memory cell;
• a first word line electrically connected to a gate of the first memory cell and a gate of the second memory cell;
• a first bit line electrically connected to the first memory cell;
• a second bit line electrically connected to the second memory cell;
• a first sense amplifier configured to determine data read from the first memory cell at a first timing in the first and second read modes;
• a second sense amplifier configured to determine data read from the second memory cell at a second timing different from the first timing in the first read mode, and to determine the data at the first timing in the second read mode;
• a delay circuit configured to generate a second signal by delaying a first signal in the first read mode;
• and
• a controller,
• wherein in the second read mode, the first sense amplifier determines the data based on the first signal, and the second sense amplifier determines the data based on the second signal, and
• the controller is configured to:
• upon receipt of a first command set, supply the second signal to the second sense amplifier with a delay with respect to the first signal supplied to the first sense amplifier, thereby executing a read operation on the first memory cell and the second memory cell in the first read mode, and
• upon receipt of a second command set, supply the second signal to the second sense amplifier without the delay with respect to the first signal supplied to the first sense amplifier, thereby executing a read operation on the first memory cell and the second memory cell in the second read mode.