US 2020/0051639 A1 · APPARATUS HAVING MEMORY ARRAYS AND HAVING TRIM REGISTERS ASSOCIATED WITH MEMORY ARRAY ACCESS OPERATION COMMANDS

Abstract

Memories include a controller that, in response to receiving a command to perform an access operation on an array of memory cells, might be configured to perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation. The controller, in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings, might be further configured to suspend the access operation, load updated trim settings for the access operation into a particular trim register of a plurality of trim registers, set updated trims for the access operation in response to the updated trim settings in the particular trim register, and resume the access operation using the updated trims.

Claims20

Dependent claims

A memory, comprising:

an array of memory cells;
a plurality of trim registers;
and
a controller for access of the array of memory cells;
wherein the controller is configured to:
in response to receiving a command to perform an access operation on the array of memory cells, perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation;
and
in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings:
suspend the access operation;
load updated trim settings for the access operation into a particular trim register of the plurality of trim registers;
set updated trims for the access operation in response to the updated trim settings in the particular trim register;
and
resume the access operation using the updated trims.

10 more elements

A memory, comprising:

an array of memory cells;
a plurality of trim registers;
and
a controller for access of the array of memory cells;
wherein the controller is configured to:
in response to receiving a command to perform an access operation on a grouping of memory cells of the array of memory cells:
set trims in response to trim settings corresponding to the command to perform the access operation;
and
perform the access operation on the grouping of memory cells using the trims;
and
in response to receiving a command to suspend the access operation while performing the access operation and receiving a command to load updated trim settings subsequent to receiving the command to suspend the access operation:
suspend the access operation;
load updated trim settings into a particular trim register of the plurality of trim registers;
set updated trims for the access operation in response to the updated trim settings of the particular trim register;
and
resume the access operation using the updated trims in response to a criteria selected from a group consisting of receiving a command to resume the suspended access operation, and completion of an intervening operation performed while the access operation is suspended.

13 more elements

A memory, comprising:

an array of memory cells;
a plurality of trim registers;
and
a controller for access of the array of memory cells;
wherein the controller is configured to:
in response to receiving a command to perform an access operation on a grouping of memory cells of the array of memory cells:
set trims in response to trim settings corresponding to the command to perform the access operation;
and
perform the access operation on the grouping of memory cells using the trims;
in response to receiving a command to suspend the access operation while performing the access operation, wherein the command to suspend the access operation is further indicative of a desire to load updated trim settings for the access operation;
load the updated trim settings into a particular trim register of the plurality of trim registers;
set updated trims for the access operation in response to the updated trim settings of the particular trim register;
and
in response to receiving a command to resume the suspended access operation:
resume the suspended access operation using the updated trims.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/654,308Filed 16 Oct 2019

Priority

21 Dec 2012

Published

13 Feb 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G11C 16/06
Electrically programmable: auxiliary circuits, e.g. for writing into memory
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters

Family

Application13/723,781Division · filed 21 Dec 2012

Application15/015,424Division · filed 4 Feb 2016

Application15/972,358Continuation · filed 7 May 2018

Application16/654,308Continuation

Application15/972,358Division

US 10,468,105 B2Related patent

US 11,031,081 B2Related patent

US 2014/0181426 A1Published application

US 2016/0155507 A1Published application

US 2018/0254086 A1Published application

US 9,257,182 B2Related patent