US 2020/0051637 A1Published application

Method for operating memory array

AssigneeMacronix International Co., Ltd.

InventorsTao-Yuan LIN, I-Chen YANG, Yao-Wen CHANG

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Abstract

A method for operating a memory array is provided. The memory array comprises a first NAND memory string comprising a ith memory cell, a i−1th memory cell, a ith word line, and a i−1th word line. The ith memory cell and the i−1th memory cell are arranged in a sequent order with a series electrical connection. The ith word line is electrically connected to the ith memory cell. The i−1th word line is electrically connected to the i−1th memory cell. The method for operating the memory array comprises in an operating time interval, performing a program inhibiting process to the ith memory cell, and simultaneously performing a first process to the ith memory cell. The program inhibiting process comprises providing a first pre-turn on voltage to the ith word line. The first process comprises providing a second pre-turn on voltage to the i−1th word line.

Claims20

Dependent claims

A method for operating a memory array, wherein the memory array comprises a first NAND memory string, a second NAND memory string, an ith word line, an i−1th word line, and an i−2th word line, each of the first NAND memory string and the second NAND memory string comprises an ith memory cell, an i−1th memory cell, and an i−2th memory cell arranged in a sequent order with a series electrical connection, both of the ith memory cells of the first NAND memory string and the second NAND memory string are electrically connected to the ith word line, both of the i−1th memory cells of the first NAND memory string and the second NAND memory string are electrically connected to the i−1th word line, both of the i−2th memory cells of the first NAND memory string and the second NAND memory string are electrically connected to the i−2th word line,

the method for operating the memory array comprises in an operating time interval, providing a first pass voltage and then a program voltage to the ith word line, providing a second pass voltage to the i−1th word line, and providing a third pass voltage to the i−2th word line, wherein the program voltage is used for programming the ith memory cell of the second NAND memory string, the second pass voltage is higher than the first pass voltage, and the second pass voltage is higher than the third pass voltage, a program inhibiting process is performed to the ith memory cell of the first NAND memory string during the operating time interval.

A method for operating a memory array, wherein the memory array comprises a first NAND memory string, the first NAND memory string comprising:

an ith memory cell, an i−1th memory cell, and an i−2th memory cell arranged in a sequent order with a series electrical connection;
an ith word line electrically connected to the ith memory cell;
an i−1th word line electrically connected to the i−1th memory cell;
and
an i−2th word line electrically connected to the i−2th memory cell,
wherein the method for operating the memory array comprises:
in an operating time interval, performing a program inhibiting process to the ith memory cell, and simultaneously performing a first process to the i−1th memory cell, wherein the program inhibiting process comprises providing a first pre-turn on voltage and then a first pass voltage to the ith word line, the first process comprises providing a second pre-turn on voltage and then a second pass voltage to the i−1th word line;
and
providing a third pass voltage to the i−2th word line during providing the second pass voltage to the i−1th word line,
wherein the second pass voltage is higher than the first pass voltage, and the second pass voltage is higher than the third pass voltage.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/057,864Filed 8 Aug 2018
Published: 13 Feb 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/14
Programming or data input circuits: circuits for erasing electrically, e.g. erase voltage switching circuits