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US 2020/0051634 A1Published application
Resistive address decoder and virtually addressed memory
AssigneeTechnion Research & Development Foundation Limited
InventorsLeonid YAVITS, Ran GINOSAR, Uri WEISER
Life of this patent
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Abstract
NAND-based content addressable memory is provided with a memory cell including two programmable resistive elements, such as memristors. These memory cells can be used to provide a programmable resistive address decoder. Such decoders can improve computer hardware performance in various ways: 1) improved translation lookaside buffers, 2) improved cache memory, and 3) by eliminating physical addresses entirely.
Claims6
An address decoder cell comprising:
- a row select transistor having a row select gate;
- a program enable transistor having an output connected to the row select gate;
- two programmable resistive elements connected in series between complementary address lines;
- wherein an intermediate node of the two programmable resistive elements is connected to the row select gate.
1 more element
A NAND content addressable memory (CAM) cell comprising:
- a row select transistor having a row select gate;
- two programmable resistive elements connected in series between complementary bit lines;
- wherein an intermediate node of the two programmable resistive elements is connected to the row select gate.
Dependencies are inferred from the claim text.