Resistive memory devices

A resistive memory device, comprising:

• a plurality of first signal lines spaced apart from one another in a first direction, the plurality of first signal lines each extending in a second direction perpendicular to the first direction;
• a plurality of second signal lines spaced apart from one another in the second direction, the plurality of second signal lines each extending in the first direction, the plurality of second signal lines spaced apart from the plurality of first signal lines in a third direction, the third direction perpendicular to both the first direction and the second direction;
• a memory cell array including a plurality of memory cells, each memory cell of the plurality of memory cells being connected at a first end to one of the plurality of first signal lines and connected at a second end to one of the plurality of second signal lines;
• a write circuit configured to supply a write current to at least one memory cell of the plurality of memory cells, such that the write current flows from a corresponding first signal line of the plurality of first signal lines to a corresponding second signal line of the plurality of second signal lines via the at least one memory cell, the write current associated with writing data in the at least one memory cell;
• and
• a read circuit configured to supply a read current to the at least one memory cell, such that the read current flows from the corresponding second signal line to the corresponding first signal line via the at least one memory cell, the read current associated with reading data stored in the at least one memory cell.

A resistive memory device, comprising:

• a memory cell array including a memory cell connected between a first signal line and a second signal line;
• an instance of control circuitry configured to generate a write control signal to control a data writing operation performed on the memory cell and a read control signal to control a data reading operation of reading data stored in the memory cell;
• a write circuit configured to supply a write current to support the data writing operation;
• a read circuit configured to supply a read current to support the data reading operation;
• a column decoder circuit configured to electrically connect the write circuit to the first signal line, based on the write control signal;
• and
• a row decoder circuit configured to electrically connect the read circuit to the second signal line, based on the read control signal.