Rram-based monotonic counter
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Lien Linus LU, Yu-Der Chih, Chung-Cheng Chou, Tong-Chern Ong
Life of this patent
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Abstract
A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.
Claims20
A circuit, comprising:
- a memory array having a plurality of memory cells;
- a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state;
- a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state;
- and
- an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.
A circuit, comprising:
- a random access memory (RRAM) device;
- a control logic circuit, coupled to the RRAM device, and configured to use a first voltage signal to cause the RRAM device to transition from a first resistance state to a second resistance state;
- and
- a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the RRAM device's transition from the first to the second resistance state;
- and
- an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.
A method, comprising:
- providing a memory cell that is in a first resistance state;
- transitioning the memory cell from the first resistance state to a second resistance state;
- incrementing a count of a counter by one in response to the memory cell's transition from the first to second resistance state;
- and
- generating an encrypted value using an updated count provided by the counter.
Dependencies are inferred from the claim text.