Non-volatile memory cell utilizing volatile switching two terminal device and a mos transistor

A method for operating a device including a memory circuit comprising a transistor and a volatile selector device comprising a first electrode and a second electrode, wherein the first electrode of the selector device is coupled to a gate of the transistor, and the volatile selector device is characterized by a low resistance state in response to a threshold voltage greater than zero applied across the first electrode and the second electrode and is characterized by a high resistance state in response to a voltage of smaller magnitude than the threshold voltage, and greater than zero, applied across the first electrode and the second electrode, the method comprising:

• applying a first voltage to the memory circuit to thereby cause the selector device to enter into the low resistance state and to thereby induce at least a first charge upon the gate of the transistor, wherein a magnitude of the first charge is in response to a magnitude of the first voltage;
• and
• removing the first voltage from the memory circuit to thereby cause the selector device to enter into the high resistance state and to thereby trap the first charge upon the gate of the transistor;
• wherein the transistor enters a first state in response to the first charge trapped upon the gate of the transistor;
• and
• wherein the transistor is characterized by a first source to drain resistance in response to the transistor being in the first state.

A semiconductor device comprising:

• a memory device comprising:
• a transistor having a gate, a source and a drain, wherein the transistor is characterized by a first source to drain resistance state and a second source to drain resistance state;
• and
• a selector device coupled to the transistor, wherein the selector device consists of:
• a selector layer, optionally one or two ion conductor layers, a first electrode and a second electrode, wherein the first electrode of the selector device is coupled to the gate of the transistor, and wherein the selector device is characterized by a low resistance state and a high resistance state;
• and
• a voltage source coupled to the memory device, wherein the voltage source is configured to provide a first voltage and a second voltage to the memory device;
• wherein when the first voltage is applied to the memory device, the selector device is characterized by the low resistance state and the transistor is characterized by the first source to drain resistance state;
• and
• wherein when the second voltage is applied to the memory device, the selector device is characterized by the low resistance state and the transistor is characterized by the second source to drain resistance state.

A method for operating a device including a memory circuit comprising a transistor and a resistance switching selector device having a high resistance state and low resistance state and comprising no more than two electrodes including a first electrode and a second electrode, wherein the first electrode of the selector device is coupled to a gate of the transistor, the method comprising:

• applying a first variable voltage to the memory circuit to thereby induce a second variable voltage at the second electrode of the selector device and to induce a third variable voltage on the gate of the transistor, wherein after a first variable voltage difference between the second variable voltage and the third variable voltage reaches a threshold voltage associated with the selector device, causing the resistance switching selector device to enter the low resistance state such that at least a first charge is induced upon the gate of the transistor in response to the third variable voltage, and wherein after the first variable voltage difference between the second variable voltage and the third variable voltage falls below the threshold voltage associated with the selector device, causing the resistance switching selector device to enter the high resistance state such that substantially the first charge remains trapped upon the gate of the transistor;
• and thereafter
• applying a read voltage to a source of the transistor;
• and
• determining a first current flow between the source of the transistor and a drain of the transistor, wherein the first current flow is in response to the read voltage and to the first charge trapped upon the gate of the transistor.