US 2020/0051629 A1 · METHODS AND SYSTEMS FOR COMPENSATING FOR DEGRADATION OF RESISTIVE MEMORY DEVICE

Abstract

A memory controller may control a resistive memory device including memory cells may control the resistive memory device to program the memory cells into a first resistance state, control the resistive memory device to read data from the memory cells that are programmed, receive bit error rates (BER) of the memory cells, occurring in a read operation, from the resistive memory device, may determine the number of program operations on the memory cells corresponding to the BER and may, based on the number of program operations that is determined, control the memory cells to be programmed into the first resistance state by using a write current having a current level higher than that of a minimum write current required for the memory cells to be changed into the first resistance state.

Claims21

Dependent claims

A method of operating a memory controller, the memory controller configured to control a resistive memory device, the resistive memory device including a plurality of memory cells, the method comprising:

controlling the resistive memory device to program the plurality of memory cells into a first resistance state;
controlling the resistive memory device to perform a read operation on the plurality of memory cells that are programmed into the first resistance state;
receiving, from the resistive memory device, an indicator that indicates a degree of degradation of the plurality of memory cells;
and
controlling, based on the indicator that indicates the degree of degradation, the plurality of memory cells to be programmed into the first resistance state based on using a write current that has a current level greater than a current level of a minimum write current that is necessary for the plurality of memory cells to be programmed into the first resistance state.

2 more elements

A resistive memory device comprising:

a memory cell array including a plurality of memory cells;
a write circuit configured to perform a write operation, by using a write current according to a control voltage, to program the plurality of memory cells into a first resistance state;
a read circuit configured to perform a read operation to read data from the plurality of memory cells that are programmed into the first resistance state;
and
a control circuit configured to count bit error rates (BER) of the plurality of memory cells that occur in the read operation and output the BER to an outside of the resistive memory device,
wherein the control circuit is configured to, in response to a control signal that is received from the outside of the resistive memory device based on the BER, control the control voltage such that the write current is increased to have a current level that is greater than a current level of a minimum write current necessary for the plurality of memory cells to be changed into the first resistance state.

3 more elements

A memory system, comprising:

a resistive memory device, the resistive memory device including
a memory cell array including a plurality of memory cells;
a write circuit configured to perform a write operation, by using a write current according to a control voltage, to program the plurality of memory cells into a first resistance state;
a read circuit configured to perform a read operation to read data from the plurality of memory cells that are programmed into the first resistance state;
and
a control circuit configured to count bit error rates (BER) of the plurality of memory cells that occur in the read operation and output the BER;
and
a memory controller configured to control the resistive memory device,
wherein the control circuit of the resistive memory device is configured to output the BER to the memory controller,
wherein the memory controller is configured to
determine a quantity of program operations on the plurality of memory cells corresponding to the BER, and
control, based on the quantity of program operations on the plurality of memory cells that is determined, the write operation such that the write current is increased to have a current level that is greater than a current level of a minimum write current necessary for the plurality of memory cells to be changed into the first resistance state.

9 more elements

Dependencies are inferred from the claim text.

Methods and systems for compensating for degradation of resistive memory device

Life of this patent

Methods and systems for compensating for degradation of resistive memory device

Life of this patent

Abstract

Claims21